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X86 table-generator and disassembler support for the AVX

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instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127644 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Sean Callanan
2011-03-15 01:23:15 +00:00
parent 4dbe200b2d
commit a21e2eae3d
7 changed files with 570 additions and 95 deletions
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61
utils/TableGen/X86DisassemblerTables.cpp
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@@ -46,9 +46,11 @@ static inline bool inheritsFrom(InstructionContext child,
case IC_OPSIZE:
return(inheritsFrom(child, IC_64BIT_OPSIZE));
case IC_XD:
return(inheritsFrom(child, IC_64BIT_XD));
return(inheritsFrom(child, IC_64BIT_XD) ||
inheritsFrom(child, IC_VEX_XD));
case IC_XS:
return(inheritsFrom(child, IC_64BIT_XS));
return(inheritsFrom(child, IC_64BIT_XS) ||
inheritsFrom(child, IC_VEX_XS));
case IC_64BIT_REXW:
return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
inheritsFrom(child, IC_64BIT_REXW_XD) ||
@@ -65,6 +67,35 @@ static inline bool inheritsFrom(InstructionContext child,
return false;
case IC_64BIT_REXW_OPSIZE:
return false;
case IC_VEX:
return(inheritsFrom(child, IC_VEX_XS) ||
inheritsFrom(child, IC_VEX_XD) ||
inheritsFrom(child, IC_VEX_L) ||
inheritsFrom(child, IC_VEX_W) ||
inheritsFrom(child, IC_VEX_OPSIZE));
case IC_VEX_XS:
return(inheritsFrom(child, IC_VEX_L_XS) ||
inheritsFrom(child, IC_VEX_W_XS));
case IC_VEX_XD:
return(inheritsFrom(child, IC_VEX_L_XD) ||
inheritsFrom(child, IC_VEX_W_XD));
case IC_VEX_L:
return(inheritsFrom(child, IC_VEX_L_XS) ||
inheritsFrom(child, IC_VEX_L_XD));
case IC_VEX_L_XS:
return false;
case IC_VEX_L_XD:
return false;
case IC_VEX_W:
return(inheritsFrom(child, IC_VEX_W_XS) ||
inheritsFrom(child, IC_VEX_W_XD) ||
inheritsFrom(child, IC_VEX_W_OPSIZE));
case IC_VEX_W_XS:
return false;
case IC_VEX_W_XD:
return false;
case IC_VEX_OPSIZE:
return inheritsFrom(child, IC_VEX_W_OPSIZE);
default:
return false;
}
@@ -461,7 +492,29 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
for (index = 0; index < 256; ++index) {
o.indent(i * 2);
if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
o << "IC_VEX_L_OPSIZE";
else if ((index & ATTR_VEXL) && (index & ATTR_XD))
o << "IC_VEX_L_XD";
else if ((index & ATTR_VEXL) && (index & ATTR_XS))
o << "IC_VEX_L_XS";
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
o << "IC_VEX_W_OPSIZE";
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
o << "IC_VEX_W_XD";
else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
o << "IC_VEX_W_XS";
else if (index & ATTR_VEXL)
o << "IC_VEX_L";
else if ((index & ATTR_VEX) && (index & ATTR_REXW))
o << "IC_VEX_W";
else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
o << "IC_VEX_OPSIZE";
else if ((index & ATTR_VEX) && (index & ATTR_XD))
o << "IC_VEX_XD";
else if ((index & ATTR_VEX) && (index & ATTR_XS))
o << "IC_VEX_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
o << "IC_64BIT_REXW_XS";
else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
o << "IC_64BIT_REXW_XD";
@@ -484,6 +537,8 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
o << "IC_XD";
else if (index & ATTR_OPSIZE)
o << "IC_OPSIZE";
else if (index & ATTR_VEX)
o << "IC_VEX";
else
o << "IC";