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Re-commit r166971. I reverted it to quickly, when buildbots didn't have a chance

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to test it with chapni's fix (-mattr=+avx).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166985 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakub Staszak 2012-10-30 00:01:57 +00:00
parent 445ba85b8d
commit a24262a0f5
2 changed files with 13 additions and 9 deletions
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8
lib/Target/X86/X86ISelLowering.cpp
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@ -6438,17 +6438,17 @@ LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) {
} }
static bool MayFoldVectorLoad(SDValue V) { static bool MayFoldVectorLoad(SDValue V) {
if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) while (V.hasOneUse() && V.getOpcode() == ISD::BITCAST)
V = V.getOperand(0); V = V.getOperand(0);
if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR)
V = V.getOperand(0); V = V.getOperand(0);
if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR && if (V.hasOneUse() && V.getOpcode() == ISD::BUILD_VECTOR &&
V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF) V.getNumOperands() == 2 && V.getOperand(1).getOpcode() == ISD::UNDEF)
// BUILD_VECTOR (load), undef // BUILD_VECTOR (load), undef
V = V.getOperand(0); V = V.getOperand(0);
if (MayFoldLoad(V))
return true; return MayFoldLoad(V);
return false;
} }
// FIXME: the version above should always be used. Since there's // FIXME: the version above should always be used. Since there's

14
test/CodeGen/X86/vec_shuffle-30.ll
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@ -1,21 +1,25 @@
; RUN: llc < %s -march=x86 -mattr=sse41 -o %t ; RUN: llc < %s -march=x86 -mattr=+avx | FileCheck %s
; RUN: grep pshufhw %t | grep -- -95 | count 1
; RUN: grep shufps %t | count 1
; RUN: not grep pslldq %t
; CHECK: test
; Test case when creating pshufhw, we incorrectly set the higher order bit ; Test case when creating pshufhw, we incorrectly set the higher order bit
; for an undef, ; for an undef,
define void @test(<8 x i16>* %dest, <8 x i16> %in) nounwind { define void @test(<8 x i16>* %dest, <8 x i16> %in) nounwind {
entry: entry:
; CHECK-NOT: vmovaps
; CHECK: vmovlpd
; CHECK: vpshufhw $-95
%0 = load <8 x i16>* %dest %0 = load <8 x i16>* %dest
%1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14> %1 = shufflevector <8 x i16> %0, <8 x i16> %in, <8 x i32> < i32 0, i32 1, i32 2, i32 3, i32 13, i32 undef, i32 14, i32 14>
store <8 x i16> %1, <8 x i16>* %dest store <8 x i16> %1, <8 x i16>* %dest
ret void ret void
} }
; CHECK: test2
; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq ; A test case where we shouldn't generate a punpckldq but a pshufd and a pslldq
define void @test2(<4 x i32>* %dest, <4 x i32> %in) nounwind { define void @test2(<4 x i32>* %dest, <4 x i32> %in) nounwind {
entry: entry:
; CHECK-NOT: pslldq
; CHECK: shufps
%0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2> %0 = shufflevector <4 x i32> %in, <4 x i32> <i32 0, i32 0, i32 0, i32 0>, <4 x i32> < i32 undef, i32 5, i32 undef, i32 2>
store <4 x i32> %0, <4 x i32>* %dest store <4 x i32> %0, <4 x i32>* %dest
ret void ret void