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[mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions

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Differential Revision: http://reviews.llvm.org/D5117


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220275 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Zoran Jovanovic 2014-10-21 08:32:40 +00:00
parent fa20aa343b
commit a245b68293
4 changed files with 50 additions and 0 deletions
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12
lib/Target/Mips/MicroMipsInstrFormats.td
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@ -41,6 +41,18 @@ class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
// MicroMIPS 16-bit Instruction Formats
//===----------------------------------------------------------------------===//
class LOGIC_FM_MM16<bits<4> funct> {
bits<3> rt;
bits<3> rs;
bits<16> Inst;
let Inst{15-10} = 0x11;
let Inst{9-6} = funct;
let Inst{5-3} = rt;
let Inst{2-0} = rs;
}
class ADDIUS5_FM_MM16 {
bits<5> rd;
bits<4> imm;

22
lib/Target/Mips/MicroMipsInstrInfo.td
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@ -90,6 +90,21 @@ class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
let mayLoad = 1;
}
class LogicRMM16<string opstr, RegisterOperand RO,
InstrItinClass Itin = NoItinerary,
SDPatternOperator OpNode = null_frag> :
MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt),
!strconcat(opstr, "\t$rt, $rs"),
[(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
let isCommutable = 1;
let Constraints = "$rt = $dst";
}
class NotMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$rt), (ins RO:$rs),
!strconcat(opstr, "\t$rt, $rs"),
[(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>;
class AddImmUS5<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm),
!strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> {
@ -182,6 +197,13 @@ let isCall = 1, hasDelaySlot = 1, Defs = [RA] in {
!strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
}
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
LOGIC_FM_MM16<0x2>;
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>,
LOGIC_FM_MM16<0x3>;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
LOGIC_FM_MM16<0x1>;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>;
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;

12
test/MC/Mips/micromips-16-bit-instructions.s
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@ -9,6 +9,10 @@
#------------------------------------------------------------------------------
# Little endian
#------------------------------------------------------------------------------
# CHECK-EL: and16 $16, $2 # encoding: [0x82,0x44]
# CHECK-EL: not16 $17, $3 # encoding: [0x0b,0x44]
# CHECK-EL: or16 $16, $4 # encoding: [0xc4,0x44]
# CHECK-EL: xor16 $17, $5 # encoding: [0x4d,0x44]
# CHECK-EL: addius5 $7, -2 # encoding: [0xfc,0x4c]
# CHECK-EL: addiusp -16 # encoding: [0xf9,0x4f]
# CHECK-EL: mfhi $9 # encoding: [0x09,0x46]
@ -25,6 +29,10 @@
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
# CHECK-EB: and16 $16, $2 # encoding: [0x44,0x82]
# CHECK-EB: not16 $17, $3 # encoding: [0x44,0x0b]
# CHECK-EB: or16 $16, $4 # encoding: [0x44,0xc4]
# CHECK-EB: xor16 $17, $5 # encoding: [0x44,0x4d]
# CHECK-EB: addius5 $7, -2 # encoding: [0x4c,0xfc]
# CHECK-EB: addiusp -16 # encoding: [0x4f,0xf9]
# CHECK-EB: mfhi $9 # encoding: [0x46,0x09]
@ -39,6 +47,10 @@
# CHECK-EB: jr16 $9 # encoding: [0x45,0x89]
# CHECK-EB: nop # encoding: [0x00,0x00,0x00,0x00]
and16 $16, $2
not16 $17, $3
or16 $16, $4
xor16 $17, $5
addius5 $7, -2
addiusp -16
mfhi $9

4
test/MC/Mips/micromips-invalid.s
View File

@ -3,3 +3,7 @@
addius5 $7, 9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
addiusp 1032 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: immediate operand value out of range
and16 $16, $8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
not16 $18, $9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
or16 $16, $10 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
xor16 $15, $5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction