mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-09 10:31:14 +00:00
Revert "[FastISel][AArch64] Don't fold instructions too aggressively into the memory operation."
Quentin pointed out that this is not the correct approach and there is a better and easier solution. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216632 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
34ea0a1de3
commit
a26b1bdcc8
@ -134,11 +134,7 @@ private:
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// Utility helper routines.
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bool isTypeLegal(Type *Ty, MVT &VT);
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bool isLoadStoreTypeLegal(Type *Ty, MVT &VT);
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bool isLegalToFoldAddress(const Value *Obj);
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bool computeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool computeAddressRecursively(const Value *Obj, Address &Addr, Type *Ty);
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bool computeAddressBase(const Value *Obj, Address &Addr);
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bool ComputeAddress(const Value *Obj, Address &Addr, Type *Ty = nullptr);
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bool ComputeCallAddress(const Value *V, Address &Addr);
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bool SimplifyAddress(Address &Addr, MVT VT);
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void AddLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
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@ -420,68 +416,9 @@ unsigned AArch64FastISel::TargetMaterializeFloatZero(const ConstantFP* CFP) {
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return FastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true);
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}
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bool AArch64FastISel::isLegalToFoldAddress(const Value *Obj) {
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// Look through BitCast, IntToPtr, and PtrToInt.
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const auto *I = dyn_cast<Instruction>(Obj)) {
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// Bail out if the result is used in a different basic block.
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if (FuncInfo.isExportedInst(I))
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return false;
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Opcode = I->getOpcode();
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U = I;
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} else if (const auto *CE = dyn_cast<ConstantExpr>(Obj)) {
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Opcode = CE->getOpcode();
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U = CE;
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}
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switch (Opcode) {
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default:
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break;
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case Instruction::BitCast:
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return isLegalToFoldAddress(U->getOperand(0));
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case Instruction::IntToPtr:
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return isLegalToFoldAddress(U->getOperand(0));
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break;
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case Instruction::PtrToInt:
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return isLegalToFoldAddress(U->getOperand(0));
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break;
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}
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// Allocas never kill their operands, so it is safe to fold it.
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if (isa<AllocaInst>(Obj) || !isa<Instruction>(Obj))
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return true;
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const auto *I = cast<Instruction>(Obj);
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// Trivial case - the memory instruction is the only user.
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if (I->hasOneUse())
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return true;
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// Check all users - if all of them are memory instructions that FastISel
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// can handle, then it is safe to fold the instruction.
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for (auto *U : I->users())
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if (!isa<LoadInst>(U) && !isa<StoreInst>(U))
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return false;
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return true;
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}
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// Computes the address to get to an object.
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bool AArch64FastISel::computeAddress(const Value *Obj, Address &Addr,
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Type *Ty) {
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// Don't fold instructions into the memory operation if their result is
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// exported to another basic block or has more than one use - except if all
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// uses are memory operations.
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if (isLegalToFoldAddress(Obj))
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return computeAddressRecursively(Obj, Addr, Ty);
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return computeAddressBase(Obj, Addr);
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}
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bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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Type *Ty) {
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bool AArch64FastISel::ComputeAddress(const Value *Obj, Address &Addr, Type *Ty)
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{
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const User *U = nullptr;
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unsigned Opcode = Instruction::UserOp1;
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if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
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@ -508,18 +445,18 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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break;
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case Instruction::BitCast: {
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// Look through bitcasts.
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return computeAddressRecursively(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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}
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case Instruction::IntToPtr: {
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// Look past no-op inttoptrs.
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if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy())
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return computeAddressRecursively(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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break;
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}
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case Instruction::PtrToInt: {
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// Look past no-op ptrtoints. Don't increment recursion level.
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// Look past no-op ptrtoints.
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if (TLI.getValueType(U->getType()) == TLI.getPointerTy())
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return computeAddressRecursively(U->getOperand(0), Addr, Ty);
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return ComputeAddress(U->getOperand(0), Addr, Ty);
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break;
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}
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case Instruction::GetElementPtr: {
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@ -561,7 +498,7 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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// Try to grab the base operand now.
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Addr.setOffset(TmpOffset);
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if (computeAddressRecursively(U->getOperand(0), Addr, Ty))
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if (ComputeAddress(U->getOperand(0), Addr, Ty))
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return true;
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// We failed, restore everything and try the other options.
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@ -582,9 +519,6 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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break;
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}
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case Instruction::Add: {
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if (!U->hasOneUse())
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break;
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// Adds of constants are common and easy enough.
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const Value *LHS = U->getOperand(0);
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const Value *RHS = U->getOperand(1);
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@ -594,21 +528,17 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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if (const ConstantInt *CI = dyn_cast<ConstantInt>(RHS)) {
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Addr.setOffset(Addr.getOffset() + (uint64_t)CI->getSExtValue());
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return computeAddressRecursively(LHS, Addr, Ty);
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return ComputeAddress(LHS, Addr, Ty);
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}
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Address Backup = Addr;
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if (computeAddressRecursively(LHS, Addr, Ty) &&
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computeAddressRecursively(RHS, Addr, Ty))
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if (ComputeAddress(LHS, Addr, Ty) && ComputeAddress(RHS, Addr, Ty))
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return true;
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Addr = Backup;
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break;
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}
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case Instruction::Shl:
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if (!U->hasOneUse())
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break;
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if (Addr.getOffsetReg())
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break;
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@ -631,10 +561,8 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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Addr.setShift(Val);
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Addr.setExtendType(AArch64_AM::LSL);
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// Only try to fold the operand if it has one use.
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if (const auto *I = dyn_cast<Instruction>(U->getOperand(0)))
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if (I->hasOneUse() &&
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(FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB))
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if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
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U = I;
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if (const auto *ZE = dyn_cast<ZExtInst>(U))
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@ -654,10 +582,6 @@ bool AArch64FastISel::computeAddressRecursively(const Value *Obj, Address &Addr,
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break;
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}
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return computeAddressBase(Obj, Addr);
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}
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bool AArch64FastISel::computeAddressBase(const Value *Obj, Address &Addr) {
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if (Addr.getReg()) {
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if (!Addr.getOffsetReg()) {
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unsigned Reg = getRegForValue(Obj);
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@ -1428,7 +1352,7 @@ bool AArch64FastISel::SelectLoad(const Instruction *I) {
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// See if we can handle this address.
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Address Addr;
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if (!computeAddress(I->getOperand(0), Addr, I->getType()))
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if (!ComputeAddress(I->getOperand(0), Addr, I->getType()))
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return false;
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unsigned ResultReg;
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@ -1545,7 +1469,7 @@ bool AArch64FastISel::SelectStore(const Instruction *I) {
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// See if we can handle this address.
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Address Addr;
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if (!computeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
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if (!ComputeAddress(I->getOperand(1), Addr, I->getOperand(0)->getType()))
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return false;
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if (!EmitStore(VT, SrcReg, Addr, createMachineMemOperandFor(I)))
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@ -2453,7 +2377,7 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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if (MTI->isVolatile())
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return false;
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// Disable inlining for memmove before calls to computeAddress. Otherwise,
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// Disable inlining for memmove before calls to ComputeAddress. Otherwise,
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// we would emit dead code because we don't currently handle memmoves.
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bool IsMemCpy = (II->getIntrinsicID() == Intrinsic::memcpy);
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if (isa<ConstantInt>(MTI->getLength()) && IsMemCpy) {
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@ -2463,8 +2387,8 @@ bool AArch64FastISel::FastLowerIntrinsicCall(const IntrinsicInst *II) {
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unsigned Alignment = MTI->getAlignment();
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if (IsMemCpySmall(Len, Alignment)) {
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Address Dest, Src;
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if (!computeAddress(MTI->getRawDest(), Dest) ||
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!computeAddress(MTI->getRawSource(), Src))
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if (!ComputeAddress(MTI->getRawDest(), Dest) ||
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!ComputeAddress(MTI->getRawSource(), Src))
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return false;
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if (TryEmitSmallMemCpy(Dest, Src, Len, Alignment))
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return true;
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@ -281,50 +281,6 @@ define i64 @load_breg_immoff_8(i64 %a) {
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ret i64 %3
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}
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; Allow folding of the address if it is used by memory instructions only.
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define void @load_breg_immoff_9(i64 %a) {
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; FAST-LABEL: load_breg_immoff_9
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; FAST: ldr {{x[0-9]+}}, [x0, #96]
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; FAST: str {{x[0-9]+}}, [x0, #96]
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%1 = add i64 %a, 96
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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%4 = add i64 %3, 1
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store i64 %4, i64* %2
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ret void
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}
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; Don't fold if the add result leaves the basic block - even if the user is a
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; memory operation.
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define i64 @load_breg_immoff_10(i64 %a, i1 %c) {
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; FAST-LABEL: load_breg_immoff_10
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; FAST: add [[REG:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 96
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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br i1 %c, label %bb1, label %bb2
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bb1:
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%4 = shl i64 %1, 3
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%5 = inttoptr i64 %4 to i64*
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%res = load i64* %5
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ret i64 %res
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bb2:
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ret i64 %3
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}
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; Don't allow folding of the address if it is used by non-memory instructions.
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define i64 @load_breg_immoff_11(i64 %a) {
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; FAST-LABEL: load_breg_immoff_11
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; FAST: add [[REG:x[0-9]+]], {{x[0-9]+}}, {{x[0-9]+}}
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, 96
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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%4 = add i64 %1, %3
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ret i64 %4
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}
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; Load Base Register + Register Offset
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define i64 @load_breg_offreg_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_offreg_1
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@ -345,33 +301,6 @@ define i64 @load_breg_offreg_2(i64 %a, i64 %b) {
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ret i64 %3
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}
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; Don't fold if the add result leaves the basic block.
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define i64 @load_breg_offreg_3(i64 %a, i64 %b, i1 %c) {
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; FAST-LABEL: load_breg_offreg_3
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; FAST: add [[REG:x[0-9]+]], x0, x1
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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br i1 %c, label %bb1, label %bb2
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bb1:
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%res = load i64* %2
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ret i64 %res
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bb2:
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ret i64 %3
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}
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define i64 @load_breg_offreg_4(i64 %a, i64 %b, i1 %c) {
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; FAST-LABEL: load_breg_offreg_4
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; FAST: add [[REG:x[0-9]+]], x0, x1
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}[[REG]]{{\]}}
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%1 = add i64 %a, %b
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%2 = inttoptr i64 %1 to i64*
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%3 = load i64* %2
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%4 = add i64 %1, %3
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ret i64 %4
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}
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; Load Base Register + Register Offset + Immediate Offset
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define i64 @load_breg_offreg_immoff_1(i64 %a, i64 %b) {
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; CHECK-LABEL: load_breg_offreg_immoff_1
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@ -476,35 +405,6 @@ define i32 @load_breg_shift_offreg_5(i64 %a, i64 %b) {
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ret i32 %5
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}
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; Don't fold if the shift result leaves the basic block.
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define i64 @load_breg_shift_offreg_6(i64 %a, i64 %b, i1 %c) {
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; FAST-LABEL: load_breg_shift_offreg_6
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; FAST: lsl [[REG:x[0-9]+]], x0, {{x[0-9]+}}
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}x1, [[REG]]{{\]}}
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%1 = shl i64 %a, 3
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%2 = add i64 %b, %1
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%3 = inttoptr i64 %2 to i64*
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%4 = load i64* %3
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br i1 %c, label %bb1, label %bb2
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bb1:
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%5 = inttoptr i64 %1 to i64*
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%res = load i64* %5
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ret i64 %res
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bb2:
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ret i64 %4
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}
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define i64 @load_breg_shift_offreg_7(i64 %a, i64 %b) {
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; FAST-LABEL: load_breg_shift_offreg_7
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; FAST: lsl [[REG:x[0-9]+]], x0, {{x[0-9]+}}
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; FAST-NEXT: ldr {{x[0-9]+}}, {{\[}}x1, [[REG]]{{\]}}
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%1 = shl i64 %a, 3
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%2 = add i64 %b, %1
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%3 = inttoptr i64 %2 to i64*
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%4 = load i64* %3
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%5 = add i64 %1, %4
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ret i64 %5
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}
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; Load Base Register + Scaled Register Offset + Sign/Zero extension
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define i32 @load_breg_zext_shift_offreg_1(i32 %a, i64 %b) {
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@ -529,36 +429,6 @@ define i32 @load_breg_zext_shift_offreg_2(i32 %a, i64 %b) {
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ret i32 %5
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}
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; Don't fold if the zext result leaves the basic block.
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define i64 @load_breg_zext_shift_offreg_3(i32 %a, i64 %b, i1 %c) {
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; FAST-LABEL: load_breg_zext_shift_offreg_3
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; FAST: ldr {{x[0-9]+}}, {{\[}}x1, {{x[0-9]+}}, lsl #3{{\]}}
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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br i1 %c, label %bb1, label %bb2
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bb1:
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%6 = inttoptr i64 %1 to i64*
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%res = load i64* %6
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ret i64 %res
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bb2:
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ret i64 %5
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}
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define i64 @load_breg_zext_shift_offreg_4(i32 %a, i64 %b) {
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; FAST-LABEL: load_breg_zext_shift_offreg_4
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; FAST: ldr {{x[0-9]+}}, {{\[}}x1, {{x[0-9]+}}, lsl #3{{\]}}
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%1 = zext i32 %a to i64
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%2 = shl i64 %1, 3
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%3 = add i64 %b, %2
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%4 = inttoptr i64 %3 to i64*
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%5 = load i64* %4
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%6 = add i64 %1, %5
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ret i64 %6
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}
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define i32 @load_breg_sext_shift_offreg_1(i32 %a, i64 %b) {
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; CHECK-LABEL: load_breg_sext_shift_offreg_1
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; CHECK: ldr {{w[0-9]+}}, [x1, w0, sxtw #2]
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