6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-14 14:24:05 +00:00
Code Issues Projects Releases Wiki Activity

Fix DisassembleThumb2DPReg()'s handling of RegClass. Cannot hardcode GPRRegClassID.

Browse Source 
Also add some test cases.

rdar://problem/9189829


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128304 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen
2011-03-25 22:19:07 +00:00
parent abeea57639
commit a2755b9829
2 changed files with 15 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

12
lib/Target/ARM/Disassembler/ThumbDisassemblerCore.h
View File

@ -1947,25 +1947,25 @@ static bool DisassembleThumb2DPReg(MCInst &MI, unsigned Opcode, uint32_t insn,
OpIdx = 0; OpIdx = 0;
assert(NumOps >= 2 && assert(NumOps >= 2 &&
OpInfo[0].RegClass == ARM::rGPRRegClassID && OpInfo[0].RegClass > 0 &&
OpInfo[1].RegClass == ARM::rGPRRegClassID && OpInfo[1].RegClass > 0 &&
"Expect >= 2 operands and first two as reg operands"); "Expect >= 2 operands and first two as reg operands");
// Build the register operands, followed by the optional rotation amount. // Build the register operands, followed by the optional rotation amount.
bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass == ARM::rGPRRegClassID; bool ThreeReg = NumOps > 2 && OpInfo[2].RegClass > 0;
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
decodeRs(insn)))); decodeRs(insn))));
++OpIdx; ++OpIdx;
if (ThreeReg) { if (ThreeReg) {
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B,OpInfo[OpIdx].RegClass,
decodeRn(insn)))); decodeRn(insn))));
++OpIdx; ++OpIdx;
} }
MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::rGPRRegClassID, MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, OpInfo[OpIdx].RegClass,
decodeRm(insn)))); decodeRm(insn))));
++OpIdx; ++OpIdx;

9
test/MC/Disassembler/ARM/thumb-tests.txt
View File

@ -172,3 +172,12 @@
# CHECK: ldr.w r5, [r6, #30] # CHECK: ldr.w r5, [r6, #30]
0x56 0xf8 0x1e 0x56 0x56 0xf8 0x1e 0x56
# CHECK: sel r7, r3, r5
0xa3 0xfa 0x85 0xf7
# CHECK: lsl.w r7, r3, r5
0x03 0xfa 0x05 0xf7
# CHECK: adds.w r7, r3, r5
0x13 0xeb 0x05 0x07