mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-26 05:32:25 +00:00
PowerPCInstrInfo and PowerPCRegisterInfo have gone away; they are replaced
by 32- and 64-bit customized files, named appropriately. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15856 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman
parent
08dde0ba85
commit
a2a27b3c85
@ -1,62 +0,0 @@
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//===- PowerPCInstrInfo.cpp - PowerPC Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPCInstrInfo.h"
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#include "PowerPC.h"
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#include "PowerPCGenInstrInfo.inc"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include <iostream>
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using namespace llvm;
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PowerPCInstrInfo::PowerPCInstrInfo(bool is64b)
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: TargetInstrInfo(PowerPCInsts, sizeof(PowerPCInsts)/sizeof(PowerPCInsts[0])),
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RI(is64b),
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is64bit(is64b)
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{ }
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bool PowerPCInstrInfo::isMoveInstr(const MachineInstr& MI,
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unsigned& sourceReg,
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unsigned& destReg) const {
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MachineOpCode oc = MI.getOpcode();
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if (oc == PPC::OR) { // or r1, r2, r2
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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MI.getOperand(2).isRegister() &&
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"invalid PPC OR instruction!");
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if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::ADDI) { // addi r1, r2, 0
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assert(MI.getNumOperands() == 3 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(2).isImmediate() &&
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"invalid PPC ADDI instruction!");
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if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImmedValue()==0) {
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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} else if (oc == PPC::FMR) { // fmr r1, r2
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assert(MI.getNumOperands() == 2 &&
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MI.getOperand(0).isRegister() &&
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MI.getOperand(1).isRegister() &&
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"invalid PPC FMR instruction");
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sourceReg = MI.getOperand(1).getReg();
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destReg = MI.getOperand(0).getReg();
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return true;
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}
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return false;
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}
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@ -1,324 +0,0 @@
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//===- PowerPCRegisterInfo.cpp - PowerPC Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the PowerPC implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "reginfo"
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#include "PowerPC.h"
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#include "PowerPCRegisterInfo.h"
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#include "PowerPCInstrBuilder.h"
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#include "llvm/Constants.h"
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#include "llvm/Type.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetOptions.h"
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#include "Support/CommandLine.h"
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#include "Support/Debug.h"
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#include "Support/STLExtras.h"
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#include <iostream>
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using namespace llvm;
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namespace llvm {
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// Switch toggling compilation for AIX
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extern cl::opt<bool> AIX;
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}
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PowerPCRegisterInfo::PowerPCRegisterInfo(bool is64b)
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: PowerPCGenRegisterInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
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is64bit(is64b) {
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ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
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ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
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ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
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ImmToIdxMap[PPC::LWZ] = PPC::LWZX; ImmToIdxMap[PPC::LWA] = PPC::LWAX;
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ImmToIdxMap[PPC::LFS] = PPC::LFSX; ImmToIdxMap[PPC::LFD] = PPC::LFDX;
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ImmToIdxMap[PPC::STH] = PPC::STHX; ImmToIdxMap[PPC::STW] = PPC::STWX;
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ImmToIdxMap[PPC::STFS] = PPC::STFSX; ImmToIdxMap[PPC::STFD] = PPC::STFDX;
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ImmToIdxMap[PPC::ADDI] = PPC::ADD;
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}
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static unsigned getIdx(const TargetRegisterClass *RC) {
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if (RC == PowerPC::GPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 1: return 0;
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case 2: return 1;
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case 4: return 2;
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case 8: return 3;
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}
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} else if (RC == PowerPC::FPRCRegisterClass) {
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switch (RC->getSize()) {
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default: assert(0 && "Invalid data size!");
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case 4: return 4;
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case 8: return 5;
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}
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}
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std::cerr << "Invalid register class to getIdx()!\n";
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abort();
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}
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void
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PowerPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx) const {
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const TargetRegisterClass *RC = getRegClass(SrcReg);
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static const unsigned Opcode[] = {
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PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD
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};
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unsigned OC = Opcode[getIdx(RC)];
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if (SrcReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(PPC::R11),FrameIdx);
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} else {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 3).addReg(SrcReg),FrameIdx);
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}
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}
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void
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PowerPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx) const{
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static const unsigned Opcode[] = {
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PPC::LBZ, PPC::LHZ, PPC::LWZ, PPC::LD, PPC::LFS, PPC::LFD
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};
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const TargetRegisterClass *RC = getRegClass(DestReg);
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unsigned OC = Opcode[getIdx(RC)];
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if (DestReg == PPC::LR) {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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} else {
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BuildMI(MBB, MI, PPC::IMPLICIT_DEF, 0, PPC::R0);
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addFrameReference(BuildMI(MBB, MI, OC, 2, DestReg), FrameIdx);
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}
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}
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void PowerPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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MachineInstr *I;
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if (RC == PowerPC::GPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
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} else if (RC == PowerPC::FPRCRegisterClass) {
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BuildMI(MBB, MI, PPC::FMR, 1, DestReg).addReg(SrcReg);
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} else {
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std::cerr << "Attempt to copy register that is not GPR or FPR";
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abort();
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}
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}
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//===----------------------------------------------------------------------===//
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// Stack Frame Processing methods
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//===----------------------------------------------------------------------===//
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// hasFP - Return true if the specified function should have a dedicated frame
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// pointer register. This is true if the function has variable sized allocas or
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// if frame pointer elimination is disabled.
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//
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static bool hasFP(MachineFunction &MF) {
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MachineFrameInfo *MFI = MF.getFrameInfo();
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return MFI->hasVarSizedObjects();
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}
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void PowerPCRegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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if (hasFP(MF)) {
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// If we have a frame pointer, convert as follows:
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// ADJCALLSTACKDOWN -> addi, r1, r1, -amount
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// ADJCALLSTACKUP -> addi, r1, r1, amount
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MachineInstr *Old = I;
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unsigned Amount = Old->getOperand(0).getImmedValue();
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if (Amount != 0) {
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// We need to keep the stack aligned properly. To do this, we round the
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// amount of space needed for the outgoing arguments up to the next
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// alignment boundary.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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Amount = (Amount+Align-1)/Align*Align;
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// Replace the pseudo instruction with a new instruction...
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if (Old->getOpcode() == PPC::ADJCALLSTACKDOWN) {
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MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
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.addSImm(-Amount));
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} else {
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assert(Old->getOpcode() == PPC::ADJCALLSTACKUP);
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MBB.insert(I, BuildMI(PPC::ADDI, 2, PPC::R1).addReg(PPC::R1)
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.addSImm(Amount));
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}
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}
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}
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MBB.erase(I);
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}
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void
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PowerPCRegisterInfo::
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eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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unsigned i = 0;
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MachineInstr &MI = *II;
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MachineBasicBlock &MBB = *MI.getParent();
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MachineFunction &MF = *MBB.getParent();
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while (!MI.getOperand(i).isFrameIndex()) {
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++i;
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assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
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}
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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MI.getOperand(OffIdx).getImmedValue();
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// If we're not using a Frame Pointer that has been set to the value of the
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// SP before having the stack size subtracted from it, then add the stack size
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// to Offset to get the correct offset.
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Offset += MF.getFrameInfo()->getStackSize();
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if (Offset > 32767 || Offset < -32768) {
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// Insert a set of r0 with the full offset value before the ld, st, or add
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MachineBasicBlock *MBB = MI.getParent();
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MBB->insert(II, BuildMI(PPC::LIS, 1, PPC::R0).addSImm(Offset >> 16));
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MBB->insert(II, BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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.addImm(Offset));
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// convert into indexed form of the instruction
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// sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
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// addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
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unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
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assert(NewOpcode && "No indexed form of load or store available!");
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MI.setOpcode(NewOpcode);
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MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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MI.SetMachineOperandReg(2, PPC::R0);
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} else {
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MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
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}
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}
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void PowerPCRegisterInfo::emitPrologue(MachineFunction &MF) const {
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MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
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MachineBasicBlock::iterator MBBI = MBB.begin();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineInstr *MI;
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// Get the number of bytes to allocate from the FrameInfo
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unsigned NumBytes = MFI->getStackSize();
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// If we have calls, we cannot use the red zone to store callee save registers
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// and we must set up a stack frame, so calculate the necessary size here.
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if (MFI->hasCalls()) {
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// We reserve argument space for call sites in the function immediately on
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// entry to the current function. This eliminates the need for add/sub
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// brackets around call sites.
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NumBytes += MFI->getMaxCallFrameSize();
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}
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// Do we need to allocate space on the stack?
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if (NumBytes == 0) return;
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// Add the size of R1 to NumBytes size for the store of R1 to the bottom
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// of the stack and round the size to a multiple of the alignment.
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unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
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unsigned R1Size = getRegClass(PPC::R1)->getSize();
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unsigned R31Size = getRegClass(PPC::R31)->getSize();
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unsigned Size = (hasFP(MF)) ? R1Size + R31Size : R1Size;
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NumBytes = (NumBytes+Size+Align-1)/Align*Align;
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// Update frame info to pretend that this is part of the stack...
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MFI->setStackSize(NumBytes);
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// adjust stack pointer: r1 -= numbytes
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if (NumBytes <= 32768) {
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unsigned StoreOp = is64bit ? PPC::STDU : PPC::STWU;
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MI = BuildMI(StoreOp, 3).addReg(PPC::R1).addSImm(-NumBytes).addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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} else {
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int NegNumbytes = -NumBytes;
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unsigned StoreOp = is64bit ? PPC::STDUX : PPC::STWUX;
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MI = BuildMI(PPC::LIS, 1, PPC::R0).addSImm(NegNumbytes >> 16);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC::ORI, 2, PPC::R0).addReg(PPC::R0)
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.addImm(NegNumbytes & 0xFFFF);
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MBB.insert(MBBI, MI);
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MI = BuildMI(StoreOp, 3).addReg(PPC::R1).addReg(PPC::R1).addReg(PPC::R0);
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MBB.insert(MBBI, MI);
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}
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if (hasFP(MF)) {
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unsigned StoreOp = is64bit ? PPC::STD : PPC::STW;
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MI = BuildMI(StoreOp, 3).addReg(PPC::R31).addSImm(R1Size).addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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MI = BuildMI(PPC::OR, 2, PPC::R31).addReg(PPC::R1).addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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}
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}
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void PowerPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = prior(MBB.end());
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MachineInstr *MI;
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assert(MBBI->getOpcode() == PPC::BLR &&
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"Can only insert epilog into returning blocks");
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// Get the number of bytes allocated from the FrameInfo...
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unsigned NumBytes = MFI->getStackSize();
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if (NumBytes != 0) {
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unsigned Opcode = is64bit ? PPC::LD : PPC::LWZ;
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unsigned Offset = is64bit ? 8 : 4;
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if (hasFP(MF)) {
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MI = BuildMI(PPC::OR, 2, PPC::R1).addReg(PPC::R31).addReg(PPC::R31);
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MBB.insert(MBBI, MI);
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MI = BuildMI(Opcode, 2, PPC::R31).addSImm(Offset).addReg(PPC::R31);
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MBB.insert(MBBI, MI);
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}
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MI = BuildMI(Opcode, 2, PPC::R1).addSImm(0).addReg(PPC::R1);
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MBB.insert(MBBI, MI);
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}
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}
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#include "PowerPCGenRegisterInfo.inc"
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const TargetRegisterClass*
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PowerPCRegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getTypeID()) {
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default: assert(0 && "Invalid type to getClass!");
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case Type::LongTyID:
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case Type::ULongTyID:
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if (!is64bit) assert(0 && "Long values can't fit in registers!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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}
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