mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-09-26 09:18:56 +00:00
Changed stack allocation On LowerFORMAL_ARGUMENTS.
Added comments about new stack allocation. Expand SelectCC for i32 results git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41527 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -15,12 +15,12 @@
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#define DEBUG_TYPE "mips-lower"
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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#include "MipsISelLowering.h"
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#include "MipsMachineFunction.h"
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#include "MipsTargetMachine.h"
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#include "MipsTargetMachine.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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#include "llvm/Function.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CallingConv.h"
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#include "llvm/ADT/VectorExtras.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunction.h"
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@@ -76,8 +76,9 @@ MipsTargetLowering(MipsTargetMachine &TM): TargetLowering(TM)
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SELECT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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// Mips not supported intrinsics.
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// Mips not supported intrinsics.
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
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@@ -224,7 +225,7 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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// To meet ABI, Mips must always allocate 16 bytes on
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// To meet ABI, Mips must always allocate 16 bytes on
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// the stack (even if less than 4 are used as arguments)
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// the stack (even if less than 4 are used as arguments)
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int VTsize = MVT::getSizeInBits(MVT::i32)/8;
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int VTsize = MVT::getSizeInBits(MVT::i32)/8;
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MFI->CreateFixedObject(VTsize, -(VTsize*3));
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MFI->CreateFixedObject(VTsize, (VTsize*3));
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CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
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CCInfo.AnalyzeCallOperands(Op.Val, CC_Mips);
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@@ -272,10 +273,10 @@ LowerCCCCallTo(SDOperand Op, SelectionDAG &DAG, unsigned CC)
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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// Create the frame index object for this incoming parameter
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// Create the frame index object for this incoming parameter
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// This guarantees that when allocating Local Area our room
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// This guarantees that when allocating Local Area the firsts
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// will not be overwritten.
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// 16 bytes which are alwayes reserved won't be overwritten.
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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-(16 + VA.getLocMemOffset()) );
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(16 + VA.getLocMemOffset()));
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SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
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SDOperand PtrOff = DAG.getFrameIndex(FI,getPointerTy());
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@@ -364,10 +365,6 @@ LowerCallResult(SDOperand Chain, SDOperand InFlag, SDNode *TheCall,
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CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
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CCInfo.AnalyzeCallResult(TheCall, RetCC_Mips);
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SmallVector<SDOperand, 8> ResultVals;
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SmallVector<SDOperand, 8> ResultVals;
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// Returns void
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//if (!RVLocs.size())
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// return Chain.Val;
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// Copy all of the result registers out of their specified physreg.
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// Copy all of the result registers out of their specified physreg.
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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for (unsigned i = 0; i != RVLocs.size(); ++i) {
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Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
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Chain = DAG.getCopyFromReg(Chain, RVLocs[i].getLocReg(),
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@@ -410,6 +407,7 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
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SDOperand Root = Op.getOperand(0);
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SDOperand Root = Op.getOperand(0);
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
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@@ -438,7 +436,6 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
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else
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else
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assert(0 && "support only Mips::CPURegsRegisterClass");
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assert(0 && "support only Mips::CPURegsRegisterClass");
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// Transform the arguments stored on
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// Transform the arguments stored on
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// physical registers into virtual ones
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// physical registers into virtual ones
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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unsigned Reg = AddLiveIn(DAG.getMachineFunction(), VA.getLocReg(), RC);
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@@ -460,17 +457,22 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
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ArgValues.push_back(ArgValue);
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ArgValues.push_back(ArgValue);
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// To meet ABI, when VARARGS are passed on registers, the registers
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// To meet ABI, when VARARGS are passed on registers, the registers
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// containt must be written to the their always reserved home location
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// must have their values written to the caller stack frame.
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// on the stack.
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if (isVarArg) {
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if (isVarArg) {
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if (StackPtr.Val == 0)
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if (StackPtr.Val == 0)
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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StackPtr = DAG.getRegister(StackReg, getPointerTy());
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// Create the frame index object for this incoming parameter
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// The stack pointer offset is relative to the caller stack frame.
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// The first 16 bytes are reserved.
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// Since the real stack size is unknown here, a negative SPOffset
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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// is used so there's a way to adjust these offsets when the stack
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i*4);
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// size get known (on EliminateFrameIndex). A dummy SPOffset is
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// used instead of a direct negative address (which is recorded to
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// be used on emitPrologue) to avoid mis-calc of the first stack
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// offset on PEI::calculateFrameObjectOffsets.
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// Arguments are always 32-bit.
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int FI = MFI->CreateFixedObject(4, 0);
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MipsFI->recordStoreVarArgsFI(FI, -(4+(i*4)));
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SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
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SDOperand PtrOff = DAG.getFrameIndex(FI, getPointerTy());
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// emit ISD::STORE whichs stores the
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// emit ISD::STORE whichs stores the
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@@ -482,9 +484,16 @@ LowerCCCArguments(SDOperand Op, SelectionDAG &DAG)
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// sanity check
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// sanity check
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assert(VA.isMemLoc());
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assert(VA.isMemLoc());
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// Create the frame index object for this incoming parameter...
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// The stack pointer offset is relative to the caller stack frame.
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int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
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// Since the real stack size is unknown here, a negative SPOffset
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(16 + VA.getLocMemOffset()));
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// is used so there's a way to adjust these offsets when the stack
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// size get known (on EliminateFrameIndex). A dummy SPOffset is
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// used instead of a direct negative address (which is recorded to
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// be used on emitPrologue) to avoid mis-calc of the first stack
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// offset on PEI::calculateFrameObjectOffsets.
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// Arguments are always 32-bit.
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int FI = MFI->CreateFixedObject(4, 0);
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MipsFI->recordLoadArgsFI(FI, -(4+(16+VA.getLocMemOffset())));
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// Create load nodes to retrieve arguments from the stack
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// Create load nodes to retrieve arguments from the stack
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
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