6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

Rename encoder methods to match naming convention.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118093 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2010-11-02 22:28:01 +00:00
parent d6e623ad15
commit a2b50b300e
3 changed files with 8 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
lib/Target/ARM/ARMCodeEmitter.cpp
View File

@ -101,9 +101,6 @@ namespace {
unsigned OpIdx);
unsigned getMachineSoImmOpValue(unsigned SoImm);
unsigned getAddrMode6RegisterOperand(const MachineInstr &MI);
unsigned getAddrMode6OffsetOperand(const MachineInstr &MI);
unsigned getAddrModeSBit(const MachineInstr &MI,
const TargetInstrDesc &TID) const;
@ -174,9 +171,9 @@ namespace {
const { return 0; }
unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getAddrMode6RegisterOperand(const MachineInstr &MI, unsigned Op)
unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getAddrMode6OffsetOperand(const MachineInstr &MI, unsigned Op)
unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
const { return 0; }
unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
unsigned Op) const { return 0; }

4
lib/Target/ARM/ARMInstrInfo.td
View File

@ -472,13 +472,13 @@ def addrmode6 : Operand<i32>,
ComplexPattern<i32, 2, "SelectAddrMode6", [], [SDNPWantParent]>{
let PrintMethod = "printAddrMode6Operand";
let MIOperandInfo = (ops GPR:$addr, i32imm);
string EncoderMethod = "getAddrMode6RegisterOperand";
string EncoderMethod = "getAddrMode6AddressOpValue";
}
def am6offset : Operand<i32> {
let PrintMethod = "printAddrMode6OffsetOperand";
let MIOperandInfo = (ops GPR);
string EncoderMethod = "getAddrMode6OffsetOperand";
string EncoderMethod = "getAddrMode6OffsetOpValue";
}
// addrmodepc := pc + reg

8
lib/Target/ARM/ARMMCCodeEmitter.cpp
View File

@ -99,8 +99,8 @@ public:
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const;
unsigned getAddrMode6OffsetOperand(const MCInst &MI, unsigned Op) const;
unsigned getAddrMode6AddressOpValue(const MCInst &MI, unsigned Op) const;
unsigned getAddrMode6OffsetOpValue(const MCInst &MI, unsigned Op) const;
unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
@ -297,7 +297,7 @@ unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI,
return Binary;
}
unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
unsigned ARMMCCodeEmitter::getAddrMode6AddressOpValue(const MCInst &MI,
unsigned Op) const {
const MCOperand &Reg = MI.getOperand(Op);
const MCOperand &Imm = MI.getOperand(Op+1);
@ -313,7 +313,7 @@ unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
return RegNo | (Align << 4);
}
unsigned ARMMCCodeEmitter::getAddrMode6OffsetOperand(const MCInst &MI,
unsigned ARMMCCodeEmitter::getAddrMode6OffsetOpValue(const MCInst &MI,
unsigned Op) const {
const MCOperand &regno = MI.getOperand(Op);
if (regno.getReg() == 0) return 0x0D;