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Merge identical code.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28274 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-13 02:11:14 +00:00
parent 70074e00a2
commit a2d079a776
1 changed files with 0 additions and 8 deletions
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8
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
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@ -3012,14 +3012,6 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
case ISD::AND: case ISD::AND:
case ISD::OR: case ISD::OR:
case ISD::XOR: case ISD::XOR:
// The input may have strange things in the top bits of the registers, but
// these operations don't care. They may have weird bits going out, but
// that too is okay if they are integer operations.
Tmp1 = PromoteOp(Node->getOperand(0));
Tmp2 = PromoteOp(Node->getOperand(1));
assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
break;
case ISD::ADD: case ISD::ADD:
case ISD::SUB: case ISD::SUB:
case ISD::MUL: case ISD::MUL: