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add a little peephole optimization. This allows us to codegen:

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int a(short i) {
        return i & 1;
}

as

_a:
        andi. r3, r3, 1
        blr

instead of:

_a:
        rlwinm r2, r3, 0, 16, 31
        andi. r3, r2, 1
        blr

on ppc.  It should also help the other risc targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21189 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-04-09 21:43:54 +00:00
parent 91277ea45c
commit a2daa8c78d
1 changed files with 11 additions and 0 deletions
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11
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
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@ -766,6 +766,17 @@ SDOperand SelectionDAG::getNode(unsigned Opcode, MVT::ValueType VT,
if (!C2) return N2; // X and 0 -> 0
if (N2C->isAllOnesValue())
return N1; // X and -1 -> X
// and (zero_extend_inreg x:16:32), 1 -> and x, 1
if (N1.getOpcode() == ISD::ZERO_EXTEND_INREG ||
N1.getOpcode() == ISD::SIGN_EXTEND_INREG) {
// If we are masking out the part of our input that was extended, just
// mask the input to the extension directly.
unsigned ExtendBits =
MVT::getSizeInBits(cast<MVTSDNode>(N1)->getExtraValueType());
if ((C2 & (~0ULL << ExtendBits)) == 0)
return getNode(ISD::AND, VT, N1.getOperand(0), N2);
}
break;
case ISD::OR:
if (!C2)return N1; // X or 0 -> X