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https://github.com/c64scene-ar/llvm-6502.git
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ARM: change implicit immediate forms of {ld,st}r{,b}t to psuedo-instructions
The implicit immediate 0 forms are assembly aliases, not distinct instruction encodings. Fix the initial implementation introduced in r198914 to an alias to avoid two separate instruction definitions for the same encoding. An InstAlias is insufficient in this case as the necessary due to the need to add a new additional operand for the implicit zero. By using the AsmPsuedoInst, fall back to the C++ code to transform the instruction to the equivalent _POST_IMM form, inserting the additional implicit immediate 0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199032 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Saleem Abdulrasool
parent
188fbacade
commit
a2fce1169d
@ -329,10 +329,10 @@ class InstThumb<AddrMode am, int sz, IndexMode im,
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// Pseudo-instructions for alternate assembly syntax (never used by codegen).
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// These are aliases that require C++ handling to convert to the target
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// instruction, while InstAliases can be handled directly by tblgen.
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class AsmPseudoInst<string asm, dag iops>
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class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
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: InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
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"", NoItinerary> {
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let OutOperandList = (outs);
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let OutOperandList = oops;
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let InOperandList = iops;
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let Pattern = [];
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let isCodeGenOnly = 0; // So we get asm matcher for it.
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@ -340,16 +340,16 @@ class AsmPseudoInst<string asm, dag iops>
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let isPseudo = 1;
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}
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class ARMAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
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Requires<[IsARM]>;
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class tAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
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Requires<[IsThumb]>;
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class t2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
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Requires<[IsThumb2]>;
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class VFP2AsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
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Requires<[HasVFP2]>;
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class NEONAsmPseudo<string asm, dag iops> : AsmPseudoInst<asm, iops>,
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Requires<[HasNEON]>;
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class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
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: AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
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class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
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: AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
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class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
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: AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
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class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
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: AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
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class NEONAsmPseudo<string asm, dag iops, dag oops = (outs)>
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: AsmPseudoInst<asm, iops, oops>, Requires<[HasNEON]>;
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// Pseudo instructions for the code generator.
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class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
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@ -2450,30 +2450,23 @@ def LDRT_POST_REG : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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class LDRTImmediate<bit has_offset, string args, dag iops>
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: AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
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def LDRT_POST_IMM
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: AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addr_offset_none:$addr, am2offset_imm:$offset),
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IndexModePost, LdFrm, IIC_iLoad_ru,
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"ldrt", args, "$addr.base = $Rn_wb", []> {
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"ldrt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> addr;
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let Inst{25} = 0;
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let Inst{23} = !if(has_offset, offset{12}, 1);
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let Inst{23} = offset{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr;
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let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
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}
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def LDRT_POST_IMM
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: LDRTImmediate<1, "\t$Rt, $addr, $offset",
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(ins addr_offset_none:$addr, am2offset_imm:$offset)> {
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def LDRT_POST_IMM_0
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: LDRTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
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def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addr_offset_none:$addr, am2offset_reg:$offset),
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IndexModePost, LdFrm, IIC_iLoad_bh_ru,
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@ -2493,30 +2486,23 @@ def LDRBT_POST_REG : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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class LDRBTImmediate<bit has_offset, string args, dag iops>
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: AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), iops,
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IndexModePost, LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", args, "$addr.base = $Rn_wb", []> {
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def LDRBT_POST_IMM
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: AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb),
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(ins addr_offset_none:$addr, am2offset_imm:$offset),
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IndexModePost, LdFrm, IIC_iLoad_bh_ru,
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"ldrbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> addr;
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let Inst{25} = 0;
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let Inst{23} = !if(has_offset, offset{12}, 1);
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let Inst{23} = offset{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr;
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let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
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}
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def LDRBT_POST_IMM
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: LDRBTImmediate<1, "\t$Rt, $addr, $offset",
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(ins addr_offset_none:$addr, am2offset_imm:$offset)> {
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def LDRBT_POST_IMM_0
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: LDRBTImmediate<0, "\t$Rt, $addr", (ins addr_offset_none:$addr)>;
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multiclass AI3ldrT<bits<4> op, string opc> {
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def i : AI3ldstidxT<op, 1, (outs GPR:$Rt, GPR:$base_wb),
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(ins addr_offset_none:$addr, postidx_imm8:$offset),
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@ -2547,6 +2533,14 @@ defm LDRHT : AI3ldrT<0b1011, "ldrht">;
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defm LDRSHT : AI3ldrT<0b1111, "ldrsht">;
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}
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def LDRT_POST
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: ARMAsmPseudo<"ldrt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
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(outs GPR:$Rt)>;
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def LDRBT_POST
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: ARMAsmPseudo<"ldrbt${q} $Rt, $addr", (ins addr_offset_none:$addr, pred:$q),
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(outs GPR:$Rt)>;
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// Store
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// Stores with truncate
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@ -2777,29 +2771,26 @@ def STRBT_POST_REG : AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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class STRBTImmediate<bit has_offset, string args, dag iops>
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: AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
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IIC_iStore_bh_ru, "strbt", args, "$addr.base = $Rn_wb", []> {
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def STRBT_POST_IMM
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: AI2ldstidx<0, 1, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
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IndexModePost, StFrm, IIC_iStore_bh_ru,
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"strbt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> addr;
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let Inst{25} = 0;
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let Inst{23} = !if(has_offset, offset{12}, 1);
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let Inst{23} = offset{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr;
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let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
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}
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def STRBT_POST_IMM
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: STRBTImmediate<1, "\t$Rt, $addr, $offset",
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(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)> {
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def STRBT_POST_IMM_0
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: STRBTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>;
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def STRBT_POST
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: ARMAsmPseudo<"strbt${q} $Rt, $addr",
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(ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
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let mayStore = 1, neverHasSideEffects = 1 in {
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def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
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@ -2821,30 +2812,27 @@ def STRT_POST_REG : AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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class STRTImmediate<bit has_offset, string args, dag iops>
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: AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb), iops, IndexModePost, StFrm,
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IIC_iStore_ru, "strt", args, "$addr.base = $Rn_wb", []> {
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def STRT_POST_IMM
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: AI2ldstidx<0, 0, 0, (outs GPR:$Rn_wb),
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(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset),
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IndexModePost, StFrm, IIC_iStore_ru,
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"strt", "\t$Rt, $addr, $offset", "$addr.base = $Rn_wb", []> {
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// {12} isAdd
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// {11-0} imm12/Rm
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bits<14> offset;
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bits<4> addr;
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let Inst{25} = 0;
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let Inst{23} = !if(has_offset, offset{12}, 1);
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let Inst{23} = offset{12};
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let Inst{21} = 1; // overwrite
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let Inst{19-16} = addr;
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let Inst{11-0} = !if(has_offset, offset{11-0}, 0);
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}
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def STRT_POST_IMM
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: STRTImmediate<1, "\t$Rt, $addr, $offset",
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(ins GPR:$Rt, addr_offset_none:$addr, am2offset_imm:$offset)> {
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let Inst{11-0} = offset{11-0};
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let DecoderMethod = "DecodeAddrMode2IdxInstruction";
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}
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def STRT_POST_IMM_0
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: STRTImmediate<0, "\t$Rt, $addr", (ins GPR:$Rt, addr_offset_none:$addr)>;
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}
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def STRT_POST
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: ARMAsmPseudo<"strt${q} $Rt, $addr",
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(ins GPR:$Rt, addr_offset_none:$addr, pred:$q)>;
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multiclass AI3strT<bits<4> op, string opc> {
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def i : AI3ldstidxT<op, 0, (outs GPR:$base_wb),
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@ -6055,6 +6055,42 @@ bool ARMAsmParser::
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processInstruction(MCInst &Inst,
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const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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switch (Inst.getOpcode()) {
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// Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
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case ARM::LDRT_POST:
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case ARM::LDRBT_POST: {
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const unsigned Opcode =
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(Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
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: ARM::LDRBT_POST_IMM;
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MCInst TmpInst;
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TmpInst.setOpcode(Opcode);
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(Inst.getOperand(2));
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TmpInst.addOperand(Inst.getOperand(3));
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Inst = TmpInst;
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return true;
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}
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// Alias for alternate form of 'str{,b}t Rt, [Rn], #imm' instruction.
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case ARM::STRT_POST:
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case ARM::STRBT_POST: {
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const unsigned Opcode =
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(Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
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: ARM::STRBT_POST_IMM;
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MCInst TmpInst;
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TmpInst.setOpcode(Opcode);
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(Inst.getOperand(0));
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TmpInst.addOperand(Inst.getOperand(1));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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TmpInst.addOperand(MCOperand::CreateImm(0));
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TmpInst.addOperand(Inst.getOperand(2));
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TmpInst.addOperand(Inst.getOperand(3));
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Inst = TmpInst;
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return true;
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}
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// Alias for alternate form of 'ADR Rd, #imm' instruction.
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case ARM::ADDri: {
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if (Inst.getOperand(1).getReg() != ARM::PC ||
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@ -4,19 +4,19 @@
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@ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
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@ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
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@ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
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@ CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]
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@ CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
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@ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
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@ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
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@ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
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@ CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]
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@ CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
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@ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
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@ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
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@ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
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@ CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]
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@ CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4]
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@ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
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@ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
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@ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
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@ CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]
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@ CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4]
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ldrt r1, [r0], r2
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ldrt r1, [r0], r2, lsr #3
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ldrt r1, [r0], #4
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@ -5,8 +5,8 @@
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0x00 0x10 0xa0 0xe4
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0x00 0x10 0xe0 0xe4
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# CHECK: ldrt r1, [r0] @ encoding: [0x00,0x10,0xb0,0xe4]
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# CHECK: ldrbt r1, [r0] @ encoding: [0x00,0x10,0xf0,0xe4]
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# CHECK: strt r1, [r0] @ encoding: [0x00,0x10,0xa0,0xe4]
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# CHECK: strbt r1, [r0] @ encoding: [0x00,0x10,0xe0,0xe4]
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# CHECK: ldrt r1, [r0], #0 @ encoding: [0x00,0x10,0xb0,0xe4]
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# CHECK: ldrbt r1, [r0], #0 @ encoding: [0x00,0x10,0xf0,0xe4]
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# CHECK: strt r1, [r0], #0 @ encoding: [0x00,0x10,0xa0,0xe4]
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# CHECK: strbt r1, [r0], #0 @ encoding: [0x00,0x10,0xe0,0xe4]
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