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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-09 13:33:17 +00:00
collect a few statistics, factor constants (constant loading and mult), fix logic operation pattern matchs, supress FP div when int dividing by a constant
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21156 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Lenharth
parent
a844b017a6
commit
a32b9e31c6
@ -39,6 +39,9 @@ namespace llvm {
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cl::opt<bool> EnableAlphaFTOI("enable-alpha-ftoi",
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cl::desc("Enable use of ftoi* and itof* instructions (ev6 and higher)"),
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cl::Hidden);
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cl::opt<bool> EnableAlphaCount("enable-alpha-count",
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cl::desc("Print estimates on live ins and outs"),
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cl::Hidden);
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}
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//===----------------------------------------------------------------------===//
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@ -353,6 +356,10 @@ class ISel : public SelectionDAGISel {
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//CCInvMap sometimes (SetNE) we have the inverse CC code for free
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std::map<SDOperand, unsigned> CCInvMap;
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int count_ins;
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int count_outs;
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bool has_sym;
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public:
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ISel(TargetMachine &TM) : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
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{}
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@ -361,9 +368,21 @@ public:
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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count_ins = 0;
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count_outs = 0;
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has_sym = false;
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// Codegen the basic block.
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ISelDAG = &DAG;
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Select(DAG.getRoot());
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if(has_sym)
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++count_ins;
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if(EnableAlphaCount)
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std::cerr << "COUNT: " << BB->getParent()->getFunction ()->getName() << " "
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<< BB->getNumber() << " "
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<< count_ins << " "
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<< count_outs << "\n";
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// Clear state used for selection.
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ExprMap.clear();
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@ -388,6 +407,27 @@ public:
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};
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}
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//Factorize a number using the list of constants
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static bool factorize(int v[], int res[], int size, uint64_t c)
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{
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bool cont = true;
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while (c != 1 && cont)
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{
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cont = false;
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for(int i = 0; i < size; ++i)
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{
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if (c % v[i] == 0)
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{
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c /= v[i];
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++res[i];
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cont=true;
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}
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}
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}
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return c == 1;
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}
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//Shamelessly adapted from PPC32
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// Structure used to return the necessary information to codegen an SDIV as
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// a multiply.
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@ -975,11 +1015,13 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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@ -1050,12 +1092,14 @@ unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(1)))
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{
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::LDS_SYM, 1, Tmp1).addConstantPoolIndex(CP->getIndex());
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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@ -1246,11 +1290,13 @@ unsigned ISel::SelectExpr(SDOperand N) {
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if (Address.getOpcode() == ISD::GlobalAddress) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 1, Result).addConstantPoolIndex(CP->getIndex());
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}
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else if(Address.getOpcode() == ISD::FrameIndex) {
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@ -1267,6 +1313,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::GlobalAddress:
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::LOAD_ADDR, 1, Result)
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.addGlobalAddress(cast<GlobalAddressSDNode>(N)->getGlobal());
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return Result;
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@ -1343,6 +1390,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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//if (GASD->getGlobal()->isExternal()) {
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//use safe calling convention
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::CALL, 1).addGlobalAddress(GASD->getGlobal(),true);
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//} else {
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//use PC relative branch call
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@ -1353,6 +1401,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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dyn_cast<ExternalSymbolSDNode>(N.getOperand(1)))
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{
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AlphaLowering.restoreGP(BB);
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has_sym = true;
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BuildMI(BB, Alpha::CALL, 1).addExternalSymbol(ESSDN->getSymbol(), true);
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} else {
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//no need to restore GP as we are doing an indirect call
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@ -1383,8 +1432,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::SIGN_EXTEND_INREG:
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{
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//do SDIV opt for all levels of ints
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if (EnableAlphaIDIV && N.getOperand(0).getOpcode() == ISD::SDIV)
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//do SDIV opt for all levels of ints if not dividing by a constant
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if (EnableAlphaIDIV && N.getOperand(0).getOpcode() == ISD::SDIV
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&& N.getOperand(0).getOperand(1).getOpcode() != ISD::Constant)
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{
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unsigned Tmp4 = MakeReg(MVT::f64);
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unsigned Tmp5 = MakeReg(MVT::f64);
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@ -1483,7 +1533,7 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case MVT::i1:
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Tmp2 = MakeReg(MVT::i64);
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BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
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BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
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BuildMI(BB, Alpha::SUBQ, 2, Result).addReg(Alpha::R31).addReg(Tmp2);
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break;
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}
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return Result;
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@ -1609,6 +1659,8 @@ unsigned ISel::SelectExpr(SDOperand N) {
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case ISD::CopyFromReg:
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{
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++count_ins;
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// Make sure we generate both values.
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if (Result != notIn)
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ExprMap[N.getValue(1)] = notIn; // Generate the token
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@ -1626,10 +1678,10 @@ unsigned ISel::SelectExpr(SDOperand N) {
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//Most of the plain arithmetic and logic share the same form, and the same
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//constant immediate test
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case ISD::OR:
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case ISD::XOR:
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//Match Not
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if (N.getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue())
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cast<ConstantSDNode>(N.getOperand(1))->getSignExtended() == -1)
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{
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Tmp1 = SelectExpr(N.getOperand(0));
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BuildMI(BB, Alpha::ORNOT, 2, Result).addReg(Alpha::R31).addReg(Tmp1);
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@ -1637,11 +1689,11 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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//Fall through
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case ISD::AND:
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case ISD::XOR:
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case ISD::OR:
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//Check operand(0) == Not
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if (N.getOperand(0).getOpcode() == ISD::OR &&
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if (N.getOperand(0).getOpcode() == ISD::XOR &&
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N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue())
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cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->getSignExtended() == -1)
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{
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switch(opcode) {
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case ISD::AND: Opc = Alpha::BIC; break;
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@ -1654,9 +1706,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
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return Result;
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}
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//Check operand(1) == Not
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if (N.getOperand(1).getOpcode() == ISD::OR &&
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if (N.getOperand(1).getOpcode() == ISD::XOR &&
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N.getOperand(1).getOperand(1).getOpcode() == ISD::Constant &&
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->isAllOnesValue())
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cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getSignExtended() == -1)
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{
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switch(opcode) {
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case ISD::AND: Opc = Alpha::BIC; break;
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@ -2044,6 +2096,7 @@ void ISel::Select(SDOperand N) {
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}
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case ISD::ImplicitDef:
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++count_ins;
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Select(N.getOperand(0));
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BuildMI(BB, Alpha::IDEF, 0, cast<RegSDNode>(N)->getReg());
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return;
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@ -2060,6 +2113,7 @@ void ISel::Select(SDOperand N) {
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return;
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case ISD::CopyToReg:
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++count_outs;
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Select(N.getOperand(0));
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Tmp1 = SelectExpr(N.getOperand(1));
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Tmp2 = cast<RegSDNode>(N)->getReg();
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@ -2074,6 +2128,7 @@ void ISel::Select(SDOperand N) {
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return;
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case ISD::RET:
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++count_outs;
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switch (N.getNumOperands()) {
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default:
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std::cerr << N.getNumOperands() << "\n";
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@ -2137,6 +2192,7 @@ void ISel::Select(SDOperand N) {
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{
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AlphaLowering.restoreGP(BB);
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Opc = GetSymVersion(Opc);
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has_sym = true;
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BuildMI(BB, Opc, 2).addReg(Tmp1).addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
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}
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else if(Address.getOpcode() == ISD::FrameIndex)
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