From a3638c0f1fd13d7c685de3f7ead39b046a604d84 Mon Sep 17 00:00:00 2001 From: Chris Lattner Date: Sun, 2 Oct 2005 07:10:55 +0000 Subject: [PATCH] Add assertions to the trivial scheduler to check that the value types match up between defs and uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23590 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/CodeGen/SelectionDAG/ScheduleDAG.cpp | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp index ca014869a0c..3a75d079b1c 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp @@ -1102,6 +1102,20 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) { unsigned VReg = EmitDAG(Op.getOperand(i)); MI->addRegOperand(VReg, MachineOperand::Use); + + // Verify that it is right. + assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(II.OpInfo[i+NumResults].RegClass && + "Don't have operand info for this instruction!"); +#ifndef NDEBUG + if (RegMap->getRegClass(VReg) != II.OpInfo[i+NumResults].RegClass) { + std::cerr << "OP: "; + Op.getOperand(i).Val->dump(&DAG); std::cerr << "\nUSE: "; + Op.Val->dump(&DAG); std::cerr << "\n"; + } +#endif + assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass && + "Register class of operand and regclass of use don't agree!"); } else if (ConstantSDNode *C = dyn_cast(Op.getOperand(i))) { MI->addZeroExtImm64Operand(C->getValue()); @@ -1129,6 +1143,13 @@ unsigned SimpleSched::EmitDAG(SDOperand Op) { "Chain and flag operands should occur at end of operand list!"); unsigned VReg = EmitDAG(Op.getOperand(i)); MI->addRegOperand(VReg, MachineOperand::Use); + + // Verify that it is right. + assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?"); + assert(II.OpInfo[i+NumResults].RegClass && + "Don't have operand info for this instruction!"); + assert(RegMap->getRegClass(VReg) == II.OpInfo[i+NumResults].RegClass && + "Register class of operand and regclass of use don't agree!"); } }