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[mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191198 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders 2013-09-23 13:40:21 +00:00
parent 915432ca13
commit a399d698a8
3 changed files with 70 additions and 4 deletions
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8
lib/Target/Mips/MipsMSAInstrInfo.td
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@ -1755,10 +1755,10 @@ class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", int_mips_pckod_h, MSA128H>;
class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", int_mips_pckod_w, MSA128W>;
class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", int_mips_pckod_d, MSA128D>;
class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", int_mips_pcnt_b, MSA128B>;
class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", int_mips_pcnt_h, MSA128H>;
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", int_mips_pcnt_w, MSA128W>;
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", int_mips_pcnt_d, MSA128D>;
class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128B>;
class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128H>;
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128W>;
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128D>;
class SAT_S_B_DESC : MSA_BIT_B_DESC_BASE<"sat_s.b", int_mips_sat_s_b, MSA128B>;
class SAT_S_H_DESC : MSA_BIT_H_DESC_BASE<"sat_s.h", int_mips_sat_s_h, MSA128H>;

6
lib/Target/Mips/MipsSEISelLowering.cpp
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@ -166,6 +166,7 @@ addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
setOperationAction(ISD::ADD, Ty, Legal);
setOperationAction(ISD::AND, Ty, Legal);
setOperationAction(ISD::CTLZ, Ty, Legal);
setOperationAction(ISD::CTPOP, Ty, Legal);
setOperationAction(ISD::MUL, Ty, Legal);
setOperationAction(ISD::OR, Ty, Legal);
setOperationAction(ISD::SDIV, Ty, Legal);
@ -1012,6 +1013,11 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
}
case Intrinsic::mips_or_v:
return lowerMSABinaryIntr(Op, DAG, ISD::OR);
case Intrinsic::mips_pcnt_b:
case Intrinsic::mips_pcnt_h:
case Intrinsic::mips_pcnt_w:
case Intrinsic::mips_pcnt_d:
return lowerMSAUnaryIntr(Op, DAG, ISD::CTPOP);
case Intrinsic::mips_sll_b:
case Intrinsic::mips_sll_h:
case Intrinsic::mips_sll_w:

60
test/CodeGen/Mips/msa/bitwise.ll
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@ -452,6 +452,62 @@ define void @srl_v2i64(<2 x i64>* %c, <2 x i64>* %a, <2 x i64>* %b) nounwind {
; CHECK: .size srl_v2i64
}
define void @ctpop_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
; CHECK: ctpop_v16i8:
%1 = load <16 x i8>* %a
; CHECK-DAG: ld.b [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <16 x i8> @llvm.ctpop.v16i8 (<16 x i8> %1)
; CHECK-DAG: pcnt.b [[R3:\$w[0-9]+]], [[R1]]
store <16 x i8> %2, <16 x i8>* %c
; CHECK-DAG: st.b [[R3]], 0($4)
ret void
; CHECK: .size ctpop_v16i8
}
define void @ctpop_v8i16(<8 x i16>* %c, <8 x i16>* %a) nounwind {
; CHECK: ctpop_v8i16:
%1 = load <8 x i16>* %a
; CHECK-DAG: ld.h [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <8 x i16> @llvm.ctpop.v8i16 (<8 x i16> %1)
; CHECK-DAG: pcnt.h [[R3:\$w[0-9]+]], [[R1]]
store <8 x i16> %2, <8 x i16>* %c
; CHECK-DAG: st.h [[R3]], 0($4)
ret void
; CHECK: .size ctpop_v8i16
}
define void @ctpop_v4i32(<4 x i32>* %c, <4 x i32>* %a) nounwind {
; CHECK: ctpop_v4i32:
%1 = load <4 x i32>* %a
; CHECK-DAG: ld.w [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <4 x i32> @llvm.ctpop.v4i32 (<4 x i32> %1)
; CHECK-DAG: pcnt.w [[R3:\$w[0-9]+]], [[R1]]
store <4 x i32> %2, <4 x i32>* %c
; CHECK-DAG: st.w [[R3]], 0($4)
ret void
; CHECK: .size ctpop_v4i32
}
define void @ctpop_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
; CHECK: ctpop_v2i64:
%1 = load <2 x i64>* %a
; CHECK-DAG: ld.d [[R1:\$w[0-9]+]], 0($5)
%2 = tail call <2 x i64> @llvm.ctpop.v2i64 (<2 x i64> %1)
; CHECK-DAG: pcnt.d [[R3:\$w[0-9]+]], [[R1]]
store <2 x i64> %2, <2 x i64>* %c
; CHECK-DAG: st.d [[R3]], 0($4)
ret void
; CHECK: .size ctpop_v2i64
}
define void @ctlz_v16i8(<16 x i8>* %c, <16 x i8>* %a) nounwind {
; CHECK: ctlz_v16i8:
@ -508,6 +564,10 @@ define void @ctlz_v2i64(<2 x i64>* %c, <2 x i64>* %a) nounwind {
; CHECK: .size ctlz_v2i64
}
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %val)
declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %val)
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %val)
declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val)
declare <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %val)
declare <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %val)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %val)