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Separate out ARM MSR instructions into M-class versions and AR-class versions. This fixes some roundtripping failures.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142618 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-10-20 21:24:38 +00:00
parent 767f8be9ee
commit a3a6f215d0
1 changed files with 42 additions and 4 deletions
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46
lib/Target/ARM/ARMInstrInfo.td
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@ -4562,8 +4562,13 @@ def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
// same and the assembly parser has no way to distinguish between them. The mask // same and the assembly parser has no way to distinguish between them. The mask
// operand contains the special register (R Bit) in bit 4 and bits 3-0 contains // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains
// the mask with the fields to be accessed in the special register. // the mask with the fields to be accessed in the special register.
def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, //
"msr", "\t$mask, $Rn", []> { // NOTE: There are separate versions of these instructions for M-class versus
// AR-class processors. M-class processors can accept a wider range of
// mask values than AR-class processors can.
def MSRm : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
"msr", "\t$mask, $Rn", []>,
Requires<[IsMClass]> {
bits<5> mask; bits<5> mask;
bits<4> Rn; bits<4> Rn;
@ -4576,8 +4581,9 @@ def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
let Inst{3-0} = Rn; let Inst{3-0} = Rn;
} }
def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, def MSRmi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
"msr", "\t$mask, $a", []> { "msr", "\t$mask, $a", []>,
Requires<[IsMClass]> {
bits<5> mask; bits<5> mask;
bits<12> a; bits<12> a;
@ -4589,6 +4595,38 @@ def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
let Inst{11-0} = a; let Inst{11-0} = a;
} }
def MSRar : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary,
"msr", "\t$mask, $Rn", []>,
Requires<[IsARClass]> {
bits<5> mask;
bits<4> Rn;
let Inst{23} = 0;
let Inst{22} = 0;
let Inst{21-20} = 0b10;
let Inst{19-18} = mask{3-2};
let Inst{17-16} = 0b00;
let Inst{15-12} = 0b1111;
let Inst{11-4} = 0b00000000;
let Inst{3-0} = Rn;
}
def MSRari : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
"msr", "\t$mask, $a", []>,
Requires<[IsARClass]> {
bits<5> mask;
bits<12> a;
let Inst{23} = 0;
let Inst{22} = 0;
let Inst{21-20} = 0b10;
let Inst{19-18} = mask{3-2};
let Inst{17-16} = 0b00;
let Inst{15-12} = 0b1111;
let Inst{11-0} = a;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// TLS Instructions // TLS Instructions
// //