From a3aa2e288287da2479be3931707c9e5ca48585a2 Mon Sep 17 00:00:00 2001
From: Chris Lattner <sabre@nondot.org>
Date: Tue, 11 Jan 2005 03:37:59 +0000
Subject: [PATCH] Fix a major bug in setcc/cmov folding, where we accidentally
 inverted the sense of the comparison.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19450 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/X86/X86ISelPattern.cpp | 22 ++++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp
index a70305a7e1c..7a1b5a6972f 100644
--- a/lib/Target/X86/X86ISelPattern.cpp
+++ b/lib/Target/X86/X86ISelPattern.cpp
@@ -379,6 +379,9 @@ unsigned ISel::ComputeRegPressure(SDOperand O) {
   unsigned &Result = RegPressureMap[N];
   if (Result) return Result;
 
+  // FIXME: Should operations like CALL (which clobber lots o regs) have a
+  // higher fixed cost??
+
   if (N->getNumOperands() == 0)
     return Result = 1;
 
@@ -771,6 +774,7 @@ void ISel::EmitSelectCC(SDOperand Cond, MVT::ValueType SVT,
   } else {
     // FIXME: CMP R, 0 -> TEST R, R
     EmitCMP(Cond.getOperand(0), Cond.getOperand(1));
+    std::swap(RTrue, RFalse);
   }
   BuildMI(BB, Opc, 2, RDest).addReg(RTrue).addReg(RFalse);
 }
@@ -1438,7 +1442,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
     return Result;
 
   case ISD::SELECT:
-    // FIXME: implement folding of setcc into select.
     if (N.getValueType() != MVT::i1 && N.getValueType() != MVT::i8) {
       if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
         Tmp2 = SelectExpr(N.getOperand(1));
@@ -1452,10 +1455,17 @@ unsigned ISel::SelectExpr(SDOperand N) {
     } else {
       // FIXME: This should not be implemented here, it should be in the generic
       // code!
-      Tmp2 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
-                                        N.getOperand(1)));
-      Tmp3 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
-                                        N.getOperand(2)));
+      if (getRegPressure(N.getOperand(1)) > getRegPressure(N.getOperand(2))) {
+        Tmp2 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
+                                          N.getOperand(1)));
+        Tmp3 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
+                                          N.getOperand(2)));
+      } else {
+        Tmp3 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
+                                          N.getOperand(2)));
+        Tmp2 = SelectExpr(CurDAG->getNode(ISD::ZERO_EXTEND, MVT::i16,
+                                          N.getOperand(1)));
+      }
       unsigned TmpReg = MakeReg(MVT::i16);
       EmitSelectCC(N.getOperand(0), MVT::i16, Tmp2, Tmp3, TmpReg);
       // FIXME: need subregs to do better than this!
@@ -1971,7 +1981,7 @@ void ISel::Select(SDOperand N) {
       default: assert(0 && "Unknown operand number!");
       case 0: Select(N.getOperand(0)); break;
       case 1: Tmp1 = SelectExpr(N.getOperand(1)); break;
-      case 2: SelectAddress(N.getOperand(2), AM);
+      case 2: SelectAddress(N.getOperand(2), AM); break;
       }
 
     addFullAddress(BuildMI(BB, Opc, 4+1), AM).addReg(Tmp1);