mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-03-27 14:32:21 +00:00
PowerPC: Use RegisterOperand instead of RegisterClass operands
In the default PowerPC assembler syntax, registers are specified simply by number, so they cannot be distinguished from immediate values (without looking at the opcode). This means that the default operand matching logic for the asm parser does not work, and we need to specify custom matchers. Since those can only be specified with RegisterOperand classes and not directly on the RegisterClass, all instructions patterns used by the asm parser need to use a RegisterOperand (instead of a RegisterClass) for all their register operands. This patch adds one RegisterOperand for each RegisterClass, using the same name as the class, just in lower case, and updates all instruction patterns to use RegisterOperand instead of RegisterClass operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ulrich Weigand
parent
730a570c8c
commit
a3acc2b6cf
lib/Target/PowerPC
@ -156,41 +156,41 @@ def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
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let usesCustomInserter = 1 in {
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let Defs = [CR0] in {
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def ATOMIC_LOAD_ADD_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
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[(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_SUB_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
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[(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_OR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
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[(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_XOR_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
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[(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_AND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
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[(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_LOAD_NAND_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
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[(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
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def ATOMIC_CMP_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
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[(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
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def ATOMIC_SWAP_I64 : Pseudo<
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(outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
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(outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
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[(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
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}
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}
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// Instructions to support atomic operations
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def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
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def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
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"ldarx $rD, $ptr", LdStLDARX,
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[(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
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let Defs = [CR0] in
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def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
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def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
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"stdcx. $rS, $dst", LdStSTDCX,
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[(PPCstcx i64:$rS, xoaddr:$dst)]>,
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isDOT;
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@ -249,23 +249,23 @@ def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
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// 64-bit CR instructions
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let Interpretation64Bit = 1 in {
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let neverHasSideEffects = 1 in {
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def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
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def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS),
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"mtcrf $FXM, $rS", BrMCRX>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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let isCodeGenOnly = 1 in
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def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
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def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
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"#MFCR8pseud", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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} // neverHasSideEffects = 1
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let neverHasSideEffects = 1 in
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def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
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def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
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"mfcr $rT", SprMFCR>,
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PPC970_MicroCode, PPC970_Unit_CRU;
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let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
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def EH_SjLj_SetJmp64 : Pseudo<(outs GPRC:$dst), (ins memr:$buf),
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def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
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"#EH_SJLJ_SETJMP64",
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[(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
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Requires<[In64BitMode]>;
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@ -280,18 +280,18 @@ let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
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// 64-bit SPR manipulation instrs.
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let Uses = [CTR8] in {
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
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"mfctr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
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"mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Pattern = [(set i64:$rT, readcyclecounter)] in
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def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
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def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
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"mfspr $rT, 268", SprMFTB>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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// Note that encoding mftb using mfspr is now the preferred form,
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@ -300,17 +300,17 @@ def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
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// the POWER3.
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let Defs = [X1], Uses = [X1] in
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def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
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def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
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[(set i64:$result,
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(PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
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let Defs = [LR8] in {
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
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"mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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let Uses = [LR8] in {
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
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"mflr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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@ -325,208 +325,208 @@ let Interpretation64Bit = 1 in {
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let neverHasSideEffects = 1 in {
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let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
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def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
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def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins symbolLo64:$imm),
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"li $rD, $imm", IntSimple,
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[(set i64:$rD, immSExt16:$imm)]>;
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def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
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def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins symbolHi64:$imm),
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"lis $rD, $imm", IntSimple,
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[(set i64:$rD, imm16ShiftedSExt:$imm)]>;
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}
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// Logical ops.
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defm NAND8: XForm_6r<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"nand", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
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defm AND8 : XForm_6r<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"and", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (and i64:$rS, i64:$rB))]>;
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defm ANDC8: XForm_6r<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"andc", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
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defm OR8 : XForm_6r<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"or", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (or i64:$rS, i64:$rB))]>;
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defm NOR8 : XForm_6r<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"nor", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
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defm ORC8 : XForm_6r<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"orc", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
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defm EQV8 : XForm_6r<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"eqv", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
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defm XOR8 : XForm_6r<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
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defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
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"xor", "$rA, $rS, $rB", IntSimple,
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[(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
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// Logical ops with immediate.
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let Defs = [CR0] in {
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def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"andi. $dst, $src1, $src2", IntGeneral,
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[(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
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isDOT;
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def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"andis. $dst, $src1, $src2", IntGeneral,
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[(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
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isDOT;
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}
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def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"ori $dst, $src1, $src2", IntSimple,
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[(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
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def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"oris $dst, $src1, $src2", IntSimple,
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[(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
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def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"xori $dst, $src1, $src2", IntSimple,
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[(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
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def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
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def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2),
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"xoris $dst, $src1, $src2", IntSimple,
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[(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
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defm ADD8 : XOForm_1r<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"add", "$rT, $rA, $rB", IntSimple,
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[(set i64:$rT, (add i64:$rA, i64:$rB))]>;
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// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
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// initial-exec thread-local storage model.
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let isCodeGenOnly = 1 in
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def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
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def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
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"add $rT, $rA, $rB@tls", IntSimple,
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[(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
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defm ADDC8 : XOForm_1rc<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"addc", "$rT, $rA, $rB", IntGeneral,
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[(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
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PPC970_DGroup_Cracked;
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let Defs = [CARRY] in
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def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"addic $rD, $rA, $imm", IntGeneral,
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[(set i64:$rD, (addc i64:$rA, immSExt16:$imm))]>;
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def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
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def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolLo64:$imm),
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"addi $rD, $rA, $imm", IntSimple,
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[(set i64:$rD, (add i64:$rA, immSExt16:$imm))]>;
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def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
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def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, symbolHi64:$imm),
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"addis $rD, $rA, $imm", IntSimple,
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[(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
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let Defs = [CARRY] in {
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def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
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def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
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"subfic $rD, $rA, $imm", IntGeneral,
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[(set i64:$rD, (subc immSExt16:$imm, i64:$rA))]>;
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defm SUBFC8 : XOForm_1r<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"subfc", "$rT, $rA, $rB", IntGeneral,
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[(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
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PPC970_DGroup_Cracked;
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}
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defm SUBF8 : XOForm_1r<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
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defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
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"subf", "$rT, $rA, $rB", IntGeneral,
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[(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
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defm NEG8 : XOForm_3r<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
|
||||
defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"neg", "$rT, $rA", IntSimple,
|
||||
[(set i64:$rT, (ineg i64:$rA))]>;
|
||||
let Uses = [CARRY] in {
|
||||
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"adde", "$rT, $rA, $rB", IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
|
||||
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
|
||||
defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"addme", "$rT, $rA", IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, -1))]>;
|
||||
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
|
||||
defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"addze", "$rT, $rA", IntGeneral,
|
||||
[(set i64:$rT, (adde i64:$rA, 0))]>;
|
||||
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"subfe", "$rT, $rA, $rB", IntGeneral,
|
||||
[(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
|
||||
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
|
||||
defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"subfme", "$rT, $rA", IntGeneral,
|
||||
[(set i64:$rT, (sube -1, i64:$rA))]>;
|
||||
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
|
||||
defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
|
||||
"subfze", "$rT, $rA", IntGeneral,
|
||||
[(set i64:$rT, (sube 0, i64:$rA))]>;
|
||||
}
|
||||
|
||||
|
||||
defm MULHD : XOForm_1r<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulhd", "$rT, $rA, $rB", IntMulHW,
|
||||
[(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
|
||||
defm MULHDU : XOForm_1r<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulhdu", "$rT, $rA, $rB", IntMulHWU,
|
||||
[(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
|
||||
}
|
||||
} // Interpretation64Bit
|
||||
|
||||
let isCompare = 1, neverHasSideEffects = 1 in {
|
||||
def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
|
||||
def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
|
||||
"cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
|
||||
def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
|
||||
def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
|
||||
"cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
|
||||
def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
|
||||
def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm),
|
||||
"cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
|
||||
def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
|
||||
def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2),
|
||||
"cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
defm SLD : XForm_6r<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
|
||||
defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"sld", "$rA, $rS, $rB", IntRotateD,
|
||||
[(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
|
||||
defm SRD : XForm_6r<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
|
||||
defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"srd", "$rA, $rS, $rB", IntRotateD,
|
||||
[(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
|
||||
defm SRAD : XForm_6rc<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
|
||||
defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
|
||||
"srad", "$rA, $rS, $rB", IntRotateD,
|
||||
[(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
|
||||
|
||||
let Interpretation64Bit = 1 in {
|
||||
defm EXTSB8 : XForm_11r<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
|
||||
defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsb", "$rA, $rS", IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
|
||||
defm EXTSH8 : XForm_11r<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
|
||||
defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsh", "$rA, $rS", IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
|
||||
} // Interpretation64Bit
|
||||
|
||||
defm EXTSW : XForm_11r<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
|
||||
defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"extsw", "$rA, $rS", IntSimple,
|
||||
[(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
|
||||
let Interpretation64Bit = 1 in
|
||||
defm EXTSW_32_64 : XForm_11r<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
|
||||
defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
|
||||
"extsw", "$rA, $rS", IntSimple,
|
||||
[(set i64:$rA, (sext i32:$rS))]>, isPPC64;
|
||||
|
||||
defm SRADI : XSForm_1rc<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
|
||||
defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
|
||||
"sradi", "$rA, $rS, $SH", IntRotateDI,
|
||||
[(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
|
||||
defm CNTLZD : XForm_11r<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
|
||||
defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"cntlzd", "$rA, $rS", IntGeneral,
|
||||
[(set i64:$rA, (ctlz i64:$rS))]>;
|
||||
defm POPCNTD : XForm_11r<31, 506, (outs G8RC:$rA), (ins G8RC:$rS),
|
||||
defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
|
||||
"popcntd", "$rA, $rS", IntGeneral,
|
||||
[(set i64:$rA, (ctpop i64:$rS))]>;
|
||||
|
||||
// popcntw also does a population count on the high 32 bits (storing the
|
||||
// results in the high 32-bits of the output). We'll ignore that here (which is
|
||||
// safe because we never separately use the high part of the 64-bit registers).
|
||||
defm POPCNTW : XForm_11r<31, 378, (outs GPRC:$rA), (ins GPRC:$rS),
|
||||
defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS),
|
||||
"popcntw", "$rA, $rS", IntGeneral,
|
||||
[(set i32:$rA, (ctpop i32:$rS))]>;
|
||||
|
||||
defm DIVD : XOForm_1r<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"divd", "$rT, $rA, $rB", IntDivD,
|
||||
[(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
|
||||
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
||||
defm DIVDU : XOForm_1r<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"divdu", "$rT, $rA, $rB", IntDivD,
|
||||
[(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
|
||||
PPC970_DGroup_First, PPC970_DGroup_Cracked;
|
||||
defm MULLD : XOForm_1r<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
|
||||
defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
|
||||
"mulld", "$rT, $rA, $rB", IntMulHD,
|
||||
[(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
|
||||
}
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
let isCommutable = 1 in {
|
||||
defm RLDIMI : MDForm_1r<30, 3, (outs G8RC:$rA),
|
||||
(ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
|
||||
(ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
[]>, isPPC64, RegConstraint<"$rSi = $rA">,
|
||||
NoEncode<"$rSi">;
|
||||
@ -534,27 +534,27 @@ defm RLDIMI : MDForm_1r<30, 3, (outs G8RC:$rA),
|
||||
|
||||
// Rotate instructions.
|
||||
defm RLDCL : MDSForm_1r<30, 8,
|
||||
(outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
|
||||
"rldcl", "$rA, $rS, $rB, $MBE", IntRotateD,
|
||||
[]>, isPPC64;
|
||||
defm RLDICL : MDForm_1r<30, 0,
|
||||
(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
defm RLDICR : MDForm_1r<30, 1,
|
||||
(outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
(outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
|
||||
"rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI,
|
||||
[]>, isPPC64;
|
||||
|
||||
let Interpretation64Bit = 1 in {
|
||||
defm RLWINM8 : MForm_2r<21, (outs G8RC:$rA),
|
||||
(ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
||||
defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
|
||||
(ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
|
||||
"rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral,
|
||||
[]>;
|
||||
|
||||
let isSelect = 1 in
|
||||
def ISEL8 : AForm_4<31, 15,
|
||||
(outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, CRBITRC:$cond),
|
||||
(outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
|
||||
"isel $rT, $rA, $rB, $cond", IntGeneral,
|
||||
[]>;
|
||||
} // Interpretation64Bit
|
||||
@ -570,21 +570,21 @@ def ISEL8 : AForm_4<31, 15,
|
||||
// Sign extending loads.
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
|
||||
def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lha $rD, $src", LdStLHA,
|
||||
[(set i64:$rD, (sextloadi16 iaddr:$src))]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
|
||||
def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
|
||||
"lwa $rD, $src", LdStLWA,
|
||||
[(set i64:$rD,
|
||||
(aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lhax $rD, $src", LdStLHA,
|
||||
[(set i64:$rD, (sextloadi16 xaddr:$src))]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lwax $rD, $src", LdStLHA,
|
||||
[(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
@ -592,7 +592,7 @@ def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
|
||||
// Update forms.
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memri:$addr),
|
||||
"lhau $rD, $addr", LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
@ -600,12 +600,12 @@ def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
// NO LWAU!
|
||||
|
||||
let Interpretation64Bit = 1 in
|
||||
def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lhaux $rD, $addr", LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lwaux $rD, $addr", LdStLHAU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
@ -616,53 +616,53 @@ def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
let Interpretation64Bit = 1 in {
|
||||
// Zero extending loads.
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
|
||||
def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lbz $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi8 iaddr:$src))]>;
|
||||
def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
|
||||
def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lhz $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi16 iaddr:$src))]>;
|
||||
def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
|
||||
def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
|
||||
"lwz $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
|
||||
|
||||
def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lbzx $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi8 xaddr:$src))]>;
|
||||
def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lhzx $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi16 xaddr:$src))]>;
|
||||
def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"lwzx $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (zextloadi32 xaddr:$src))]>;
|
||||
|
||||
|
||||
// Update forms.
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lbzu $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lhzu $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
|
||||
"lwzu $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
|
||||
def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lbzux $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lhzux $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
NoEncode<"$ea_result">;
|
||||
def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"lwzux $rD, $addr", LdStLoadUpd,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
@ -674,28 +674,28 @@ def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
|
||||
// Full 8-byte loads.
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in {
|
||||
def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
|
||||
def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
|
||||
"ld $rD, $src", LdStLD,
|
||||
[(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
|
||||
// The following three definitions are selected for small code model only.
|
||||
// Otherwise, we need to create two instructions to form a 32-bit offset,
|
||||
// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
|
||||
def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
|
||||
def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
|
||||
"#LDtoc",
|
||||
[(set i64:$rD,
|
||||
(PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
|
||||
def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
|
||||
def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
|
||||
"#LDtocJTI",
|
||||
[(set i64:$rD,
|
||||
(PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
|
||||
def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
|
||||
def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
|
||||
"#LDtocCPT",
|
||||
[(set i64:$rD,
|
||||
(PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
|
||||
|
||||
let hasSideEffects = 1, isCodeGenOnly = 1 in {
|
||||
let RST = 2, DS = 2 in
|
||||
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
|
||||
def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg),
|
||||
"ld 2, 8($reg)", LdStLD,
|
||||
[(PPCload_toc i64:$reg)]>, isPPC64;
|
||||
|
||||
@ -704,20 +704,20 @@ def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
|
||||
"ld 2, 40(1)", LdStLD,
|
||||
[(PPCtoc_restore)]>, isPPC64;
|
||||
}
|
||||
def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"ldx $rD, $src", LdStLD,
|
||||
[(set i64:$rD, (load xaddr:$src))]>, isPPC64;
|
||||
def LDBRX : XForm_1<31, 532, (outs G8RC:$rD), (ins memrr:$src),
|
||||
def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
|
||||
"ldbrx $rD, $src", LdStLoad,
|
||||
[(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
|
||||
|
||||
let mayLoad = 1, neverHasSideEffects = 1 in {
|
||||
def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
|
||||
def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
|
||||
"ldu $rD, $addr", LdStLDU,
|
||||
[]>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
|
||||
NoEncode<"$ea_result">;
|
||||
|
||||
def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
|
||||
def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
|
||||
(ins memrr:$addr),
|
||||
"ldux $rD, $addr", LdStLDU,
|
||||
[]>, RegConstraint<"$addr.ptrreg = $ea_result">,
|
||||
@ -731,71 +731,71 @@ def : Pat<(PPCload xaddr:$src),
|
||||
(LDX xaddr:$src)>;
|
||||
|
||||
// Support for medium and large code model.
|
||||
def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
|
||||
def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
|
||||
"#ADDIStocHA",
|
||||
[(set i64:$rD,
|
||||
(PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
|
||||
isPPC64;
|
||||
def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC_NOX0:$reg),
|
||||
def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
|
||||
"#LDtocL",
|
||||
[(set i64:$rD,
|
||||
(PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
|
||||
def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, tocentry:$disp),
|
||||
def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
|
||||
"#ADDItocL",
|
||||
[(set i64:$rD,
|
||||
(PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
|
||||
|
||||
// Support for thread-local storage.
|
||||
def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
|
||||
def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
|
||||
"#ADDISgotTprelHA",
|
||||
[(set i64:$rD,
|
||||
(PPCaddisGotTprelHA i64:$reg,
|
||||
tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC_NOX0:$reg),
|
||||
def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins symbolLo64:$disp, g8rc_nox0:$reg),
|
||||
"#LDgotTprelL",
|
||||
[(set i64:$rD,
|
||||
(PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
|
||||
isPPC64;
|
||||
def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
|
||||
(ADD8TLS $in, tglobaltlsaddr:$g)>;
|
||||
def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
|
||||
def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
|
||||
"#ADDIStlsgdHA",
|
||||
[(set i64:$rD,
|
||||
(PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
|
||||
def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
|
||||
"#ADDItlsgdL",
|
||||
[(set i64:$rD,
|
||||
(PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
|
||||
def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
|
||||
"#GETtlsADDR",
|
||||
[(set i64:$rD,
|
||||
(PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
|
||||
isPPC64;
|
||||
def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
|
||||
def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
|
||||
"#ADDIStlsldHA",
|
||||
[(set i64:$rD,
|
||||
(PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
|
||||
def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
|
||||
"#ADDItlsldL",
|
||||
[(set i64:$rD,
|
||||
(PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
|
||||
def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
|
||||
"#GETtlsldADDR",
|
||||
[(set i64:$rD,
|
||||
(PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
|
||||
isPPC64;
|
||||
def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolHi64:$disp),
|
||||
def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolHi64:$disp),
|
||||
"#ADDISdtprelHA",
|
||||
[(set i64:$rD,
|
||||
(PPCaddisDtprelHA i64:$reg,
|
||||
tglobaltlsaddr:$disp))]>,
|
||||
isPPC64;
|
||||
def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp),
|
||||
def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, symbolLo64:$disp),
|
||||
"#ADDIdtprelL",
|
||||
[(set i64:$rD,
|
||||
(PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
|
||||
@ -804,38 +804,38 @@ def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC_NOX0:$reg, symbolLo64:$disp)
|
||||
let PPC970_Unit = 2 in {
|
||||
let Interpretation64Bit = 1 in {
|
||||
// Truncating stores.
|
||||
def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
|
||||
def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"stb $rS, $src", LdStStore,
|
||||
[(truncstorei8 i64:$rS, iaddr:$src)]>;
|
||||
def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
|
||||
def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"sth $rS, $src", LdStStore,
|
||||
[(truncstorei16 i64:$rS, iaddr:$src)]>;
|
||||
def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
|
||||
def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
|
||||
"stw $rS, $src", LdStStore,
|
||||
[(truncstorei32 i64:$rS, iaddr:$src)]>;
|
||||
def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stbx $rS, $dst", LdStStore,
|
||||
[(truncstorei8 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"sthx $rS, $dst", LdStStore,
|
||||
[(truncstorei16 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stwx $rS, $dst", LdStStore,
|
||||
[(truncstorei32 i64:$rS, xaddr:$dst)]>,
|
||||
PPC970_DGroup_Cracked;
|
||||
} // Interpretation64Bit
|
||||
|
||||
// Normal 8-byte stores.
|
||||
def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
|
||||
def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
|
||||
"std $rS, $dst", LdStSTD,
|
||||
[(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
|
||||
def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdx $rS, $dst", LdStSTD,
|
||||
[(store i64:$rS, xaddr:$dst)]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STDBRX: XForm_8<31, 660, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdbrx $rS, $dst", LdStStore,
|
||||
[(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
|
||||
PPC970_DGroup_Cracked;
|
||||
@ -844,35 +844,35 @@ def STDBRX: XForm_8<31, 660, (outs), (ins G8RC:$rS, memrr:$dst),
|
||||
// Stores with Update (pre-inc).
|
||||
let PPC970_Unit = 2, mayStore = 1 in {
|
||||
let Interpretation64Bit = 1 in {
|
||||
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"stbu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"sthu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
|
||||
def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
|
||||
"stwu $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
|
||||
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
|
||||
def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
|
||||
"stdu $rS, $dst", LdStSTDU, []>,
|
||||
RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
|
||||
isPPC64;
|
||||
|
||||
def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stbux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"sthux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stwux $rS, $dst", LdStStoreUpd, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked;
|
||||
} // Interpretation64Bit
|
||||
|
||||
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
|
||||
def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
|
||||
"stdux $rS, $dst", LdStSTDU, []>,
|
||||
RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
|
||||
PPC970_DGroup_Cracked, isPPC64;
|
||||
@ -907,26 +907,26 @@ def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
|
||||
|
||||
let PPC970_Unit = 3, neverHasSideEffects = 1,
|
||||
Uses = [RM] in { // FPU Operations.
|
||||
defm FCFID : XForm_26r<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
|
||||
defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fcfid", "$frD, $frB", FPGeneral,
|
||||
[(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
|
||||
defm FCTIDZ : XForm_26r<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
|
||||
defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctidz", "$frD, $frB", FPGeneral,
|
||||
[(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
|
||||
|
||||
defm FCFIDU : XForm_26r<63, 974, (outs F8RC:$frD), (ins F8RC:$frB),
|
||||
defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fcfidu", "$frD, $frB", FPGeneral,
|
||||
[(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
|
||||
defm FCFIDS : XForm_26r<59, 846, (outs F4RC:$frD), (ins F8RC:$frB),
|
||||
defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
|
||||
"fcfids", "$frD, $frB", FPGeneral,
|
||||
[(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
|
||||
defm FCFIDUS : XForm_26r<59, 974, (outs F4RC:$frD), (ins F8RC:$frB),
|
||||
defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
|
||||
"fcfidus", "$frD, $frB", FPGeneral,
|
||||
[(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
|
||||
defm FCTIDUZ : XForm_26r<63, 943, (outs F8RC:$frD), (ins F8RC:$frB),
|
||||
defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctiduz", "$frD, $frB", FPGeneral,
|
||||
[(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
|
||||
defm FCTIWUZ : XForm_26r<63, 143, (outs F8RC:$frD), (ins F8RC:$frB),
|
||||
defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
|
||||
"fctiwuz", "$frD, $frB", FPGeneral,
|
||||
[(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
|
||||
}
|
||||
|
||||
@ -163,7 +163,7 @@ def vecspltisw : PatLeaf<(build_vector), [{
|
||||
|
||||
// VA1a_Int_Ty - A VAForm_1a intrinsic definition of specific type.
|
||||
class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
|
||||
: VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
|
||||
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
|
||||
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
|
||||
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB, Ty:$vC))]>;
|
||||
|
||||
@ -171,7 +171,7 @@ class VA1a_Int_Ty<bits<6> xo, string opc, Intrinsic IntID, ValueType Ty>
|
||||
// inputs doesn't match the type of the output.
|
||||
class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
ValueType InTy>
|
||||
: VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
|
||||
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
|
||||
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
|
||||
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB, InTy:$vC))]>;
|
||||
|
||||
@ -179,14 +179,14 @@ class VA1a_Int_Ty2<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
// input types and an output type.
|
||||
class VA1a_Int_Ty3<bits<6> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
ValueType In1Ty, ValueType In2Ty>
|
||||
: VAForm_1a<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, VRRC:$vC),
|
||||
: VAForm_1a<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, vrrc:$vC),
|
||||
!strconcat(opc, " $vD, $vA, $vB, $vC"), VecFP,
|
||||
[(set OutTy:$vD,
|
||||
(IntID In1Ty:$vA, In1Ty:$vB, In2Ty:$vC))]>;
|
||||
|
||||
// VX1_Int_Ty - A VXForm_1 intrinsic definition of specific type.
|
||||
class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
|
||||
: VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
!strconcat(opc, " $vD, $vA, $vB"), VecFP,
|
||||
[(set Ty:$vD, (IntID Ty:$vA, Ty:$vB))]>;
|
||||
|
||||
@ -194,7 +194,7 @@ class VX1_Int_Ty<bits<11> xo, string opc, Intrinsic IntID, ValueType Ty>
|
||||
// inputs doesn't match the type of the output.
|
||||
class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
ValueType InTy>
|
||||
: VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
!strconcat(opc, " $vD, $vA, $vB"), VecFP,
|
||||
[(set OutTy:$vD, (IntID InTy:$vA, InTy:$vB))]>;
|
||||
|
||||
@ -202,13 +202,13 @@ class VX1_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
// input types and an output type.
|
||||
class VX1_Int_Ty3<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
ValueType In1Ty, ValueType In2Ty>
|
||||
: VXForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
: VXForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
!strconcat(opc, " $vD, $vA, $vB"), VecFP,
|
||||
[(set OutTy:$vD, (IntID In1Ty:$vA, In2Ty:$vB))]>;
|
||||
|
||||
// VX2_Int_SP - A VXForm_2 intrinsic definition of vector single-precision type.
|
||||
class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
|
||||
: VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
!strconcat(opc, " $vD, $vB"), VecFP,
|
||||
[(set v4f32:$vD, (IntID v4f32:$vB))]>;
|
||||
|
||||
@ -216,7 +216,7 @@ class VX2_Int_SP<bits<11> xo, string opc, Intrinsic IntID>
|
||||
// inputs doesn't match the type of the output.
|
||||
class VX2_Int_Ty2<bits<11> xo, string opc, Intrinsic IntID, ValueType OutTy,
|
||||
ValueType InTy>
|
||||
: VXForm_2<xo, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
: VXForm_2<xo, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
!strconcat(opc, " $vD, $vB"), VecFP,
|
||||
[(set OutTy:$vD, (IntID InTy:$vB))]>;
|
||||
|
||||
@ -234,93 +234,93 @@ def DSSALL : DSS_Form<822, (outs),
|
||||
(ins u5imm:$ONE, u5imm:$ZERO0,u5imm:$ZERO1,u5imm:$ZERO2),
|
||||
"dssall", LdStLoad /*FIXME*/, []>;
|
||||
def DST : DSS_Form<342, (outs),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
|
||||
"dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTT : DSS_Form<342, (outs),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
|
||||
"dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTST : DSS_Form<374, (outs),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, gprc:$rA, gprc:$rB),
|
||||
"dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTSTT : DSS_Form<374, (outs),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, gprc:$rA, gprc:$rB),
|
||||
"dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
|
||||
def DST64 : DSS_Form<342, (outs),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
|
||||
"dst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTT64 : DSS_Form<342, (outs),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
|
||||
"dstt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTST64 : DSS_Form<374, (outs),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ZERO, u5imm:$STRM, g8rc:$rA, gprc:$rB),
|
||||
"dstst $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
def DSTSTT64 : DSS_Form<374, (outs),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, G8RC:$rA, GPRC:$rB),
|
||||
(ins u5imm:$ONE, u5imm:$STRM, g8rc:$rA, gprc:$rB),
|
||||
"dststt $rA, $rB, $STRM", LdStLoad /*FIXME*/, []>;
|
||||
}
|
||||
|
||||
def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
|
||||
def MFVSCR : VXForm_4<1540, (outs vrrc:$vD), (ins),
|
||||
"mfvscr $vD", LdStStore,
|
||||
[(set v8i16:$vD, (int_ppc_altivec_mfvscr))]>;
|
||||
def MTVSCR : VXForm_5<1604, (outs), (ins VRRC:$vB),
|
||||
def MTVSCR : VXForm_5<1604, (outs), (ins vrrc:$vB),
|
||||
"mtvscr $vB", LdStLoad,
|
||||
[(int_ppc_altivec_mtvscr v4i32:$vB)]>;
|
||||
|
||||
let canFoldAsLoad = 1, PPC970_Unit = 2 in { // Loads.
|
||||
def LVEBX: XForm_1<31, 7, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVEBX: XForm_1<31, 7, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvebx $vD, $src", LdStLoad,
|
||||
[(set v16i8:$vD, (int_ppc_altivec_lvebx xoaddr:$src))]>;
|
||||
def LVEHX: XForm_1<31, 39, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVEHX: XForm_1<31, 39, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvehx $vD, $src", LdStLoad,
|
||||
[(set v8i16:$vD, (int_ppc_altivec_lvehx xoaddr:$src))]>;
|
||||
def LVEWX: XForm_1<31, 71, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVEWX: XForm_1<31, 71, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvewx $vD, $src", LdStLoad,
|
||||
[(set v4i32:$vD, (int_ppc_altivec_lvewx xoaddr:$src))]>;
|
||||
def LVX : XForm_1<31, 103, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVX : XForm_1<31, 103, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvx $vD, $src", LdStLoad,
|
||||
[(set v4i32:$vD, (int_ppc_altivec_lvx xoaddr:$src))]>;
|
||||
def LVXL : XForm_1<31, 359, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVXL : XForm_1<31, 359, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvxl $vD, $src", LdStLoad,
|
||||
[(set v4i32:$vD, (int_ppc_altivec_lvxl xoaddr:$src))]>;
|
||||
}
|
||||
|
||||
def LVSL : XForm_1<31, 6, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVSL : XForm_1<31, 6, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvsl $vD, $src", LdStLoad,
|
||||
[(set v16i8:$vD, (int_ppc_altivec_lvsl xoaddr:$src))]>,
|
||||
PPC970_Unit_LSU;
|
||||
def LVSR : XForm_1<31, 38, (outs VRRC:$vD), (ins memrr:$src),
|
||||
def LVSR : XForm_1<31, 38, (outs vrrc:$vD), (ins memrr:$src),
|
||||
"lvsr $vD, $src", LdStLoad,
|
||||
[(set v16i8:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
|
||||
PPC970_Unit_LSU;
|
||||
|
||||
let PPC970_Unit = 2 in { // Stores.
|
||||
def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
|
||||
def STVEBX: XForm_8<31, 135, (outs), (ins vrrc:$rS, memrr:$dst),
|
||||
"stvebx $rS, $dst", LdStStore,
|
||||
[(int_ppc_altivec_stvebx v16i8:$rS, xoaddr:$dst)]>;
|
||||
def STVEHX: XForm_8<31, 167, (outs), (ins VRRC:$rS, memrr:$dst),
|
||||
def STVEHX: XForm_8<31, 167, (outs), (ins vrrc:$rS, memrr:$dst),
|
||||
"stvehx $rS, $dst", LdStStore,
|
||||
[(int_ppc_altivec_stvehx v8i16:$rS, xoaddr:$dst)]>;
|
||||
def STVEWX: XForm_8<31, 199, (outs), (ins VRRC:$rS, memrr:$dst),
|
||||
def STVEWX: XForm_8<31, 199, (outs), (ins vrrc:$rS, memrr:$dst),
|
||||
"stvewx $rS, $dst", LdStStore,
|
||||
[(int_ppc_altivec_stvewx v4i32:$rS, xoaddr:$dst)]>;
|
||||
def STVX : XForm_8<31, 231, (outs), (ins VRRC:$rS, memrr:$dst),
|
||||
def STVX : XForm_8<31, 231, (outs), (ins vrrc:$rS, memrr:$dst),
|
||||
"stvx $rS, $dst", LdStStore,
|
||||
[(int_ppc_altivec_stvx v4i32:$rS, xoaddr:$dst)]>;
|
||||
def STVXL : XForm_8<31, 487, (outs), (ins VRRC:$rS, memrr:$dst),
|
||||
def STVXL : XForm_8<31, 487, (outs), (ins vrrc:$rS, memrr:$dst),
|
||||
"stvxl $rS, $dst", LdStStore,
|
||||
[(int_ppc_altivec_stvxl v4i32:$rS, xoaddr:$dst)]>;
|
||||
}
|
||||
|
||||
let PPC970_Unit = 5 in { // VALU Operations.
|
||||
// VA-Form instructions. 3-input AltiVec ops.
|
||||
def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
|
||||
def VMADDFP : VAForm_1<46, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
|
||||
"vmaddfp $vD, $vA, $vC, $vB", VecFP,
|
||||
[(set v4f32:$vD,
|
||||
(fma v4f32:$vA, v4f32:$vC, v4f32:$vB))]>;
|
||||
|
||||
// FIXME: The fma+fneg pattern won't match because fneg is not legal.
|
||||
def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
|
||||
def VNMSUBFP: VAForm_1<47, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vC, vrrc:$vB),
|
||||
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
|
||||
[(set v4f32:$vD, (fneg (fma v4f32:$vA, v4f32:$vC,
|
||||
(fneg v4f32:$vB))))]>;
|
||||
@ -335,23 +335,23 @@ def VPERM : VA1a_Int_Ty3<43, "vperm", int_ppc_altivec_vperm,
|
||||
def VSEL : VA1a_Int_Ty<42, "vsel", int_ppc_altivec_vsel, v4i32>;
|
||||
|
||||
// Shuffles.
|
||||
def VSLDOI : VAForm_2<44, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB, u5imm:$SH),
|
||||
def VSLDOI : VAForm_2<44, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB, u5imm:$SH),
|
||||
"vsldoi $vD, $vA, $vB, $SH", VecFP,
|
||||
[(set v16i8:$vD,
|
||||
(vsldoi_shuffle:$SH v16i8:$vA, v16i8:$vB))]>;
|
||||
|
||||
// VX-Form instructions. AltiVec arithmetic ops.
|
||||
def VADDFP : VXForm_1<10, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VADDFP : VXForm_1<10, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vaddfp $vD, $vA, $vB", VecFP,
|
||||
[(set v4f32:$vD, (fadd v4f32:$vA, v4f32:$vB))]>;
|
||||
|
||||
def VADDUBM : VXForm_1<0, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VADDUBM : VXForm_1<0, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vaddubm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v16i8:$vD, (add v16i8:$vA, v16i8:$vB))]>;
|
||||
def VADDUHM : VXForm_1<64, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VADDUHM : VXForm_1<64, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vadduhm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v8i16:$vD, (add v8i16:$vA, v8i16:$vB))]>;
|
||||
def VADDUWM : VXForm_1<128, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VADDUWM : VXForm_1<128, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vadduwm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v4i32:$vD, (add v4i32:$vA, v4i32:$vB))]>;
|
||||
|
||||
@ -364,27 +364,27 @@ def VADDUHS : VX1_Int_Ty<576, "vadduhs", int_ppc_altivec_vadduhs, v8i16>;
|
||||
def VADDUWS : VX1_Int_Ty<640, "vadduws", int_ppc_altivec_vadduws, v4i32>;
|
||||
|
||||
|
||||
def VAND : VXForm_1<1028, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VAND : VXForm_1<1028, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vand $vD, $vA, $vB", VecFP,
|
||||
[(set v4i32:$vD, (and v4i32:$vA, v4i32:$vB))]>;
|
||||
def VANDC : VXForm_1<1092, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VANDC : VXForm_1<1092, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vandc $vD, $vA, $vB", VecFP,
|
||||
[(set v4i32:$vD, (and v4i32:$vA,
|
||||
(vnot_ppc v4i32:$vB)))]>;
|
||||
|
||||
def VCFSX : VXForm_1<842, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VCFSX : VXForm_1<842, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vcfsx $vD, $vB, $UIMM", VecFP,
|
||||
[(set v4f32:$vD,
|
||||
(int_ppc_altivec_vcfsx v4i32:$vB, imm:$UIMM))]>;
|
||||
def VCFUX : VXForm_1<778, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VCFUX : VXForm_1<778, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vcfux $vD, $vB, $UIMM", VecFP,
|
||||
[(set v4f32:$vD,
|
||||
(int_ppc_altivec_vcfux v4i32:$vB, imm:$UIMM))]>;
|
||||
def VCTSXS : VXForm_1<970, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VCTSXS : VXForm_1<970, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vctsxs $vD, $vB, $UIMM", VecFP,
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vctsxs v4f32:$vB, imm:$UIMM))]>;
|
||||
def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VCTUXS : VXForm_1<906, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vctuxs $vD, $vB, $UIMM", VecFP,
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vctuxs v4f32:$vB, imm:$UIMM))]>;
|
||||
@ -393,19 +393,19 @@ def VCTUXS : VXForm_1<906, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
// to integer (fp_to_sint/fp_to_uint) conversions and integer
|
||||
// to floating-point (sint_to_fp/uint_to_fp) conversions.
|
||||
let VA = 0 in {
|
||||
def VCFSX_0 : VXForm_1<842, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
def VCFSX_0 : VXForm_1<842, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
"vcfsx $vD, $vB, 0", VecFP,
|
||||
[(set v4f32:$vD,
|
||||
(int_ppc_altivec_vcfsx v4i32:$vB, 0))]>;
|
||||
def VCTUXS_0 : VXForm_1<906, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
def VCTUXS_0 : VXForm_1<906, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
"vctuxs $vD, $vB, 0", VecFP,
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vctuxs v4f32:$vB, 0))]>;
|
||||
def VCFUX_0 : VXForm_1<778, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
def VCFUX_0 : VXForm_1<778, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
"vcfux $vD, $vB, 0", VecFP,
|
||||
[(set v4f32:$vD,
|
||||
(int_ppc_altivec_vcfux v4i32:$vB, 0))]>;
|
||||
def VCTSXS_0 : VXForm_1<970, (outs VRRC:$vD), (ins VRRC:$vB),
|
||||
def VCTSXS_0 : VXForm_1<970, (outs vrrc:$vD), (ins vrrc:$vB),
|
||||
"vctsxs $vD, $vB, 0", VecFP,
|
||||
[(set v4i32:$vD,
|
||||
(int_ppc_altivec_vctsxs v4f32:$vB, 0))]>;
|
||||
@ -435,22 +435,22 @@ def VMINUB : VX1_Int_Ty< 514, "vminub", int_ppc_altivec_vminub, v16i8>;
|
||||
def VMINUH : VX1_Int_Ty< 578, "vminuh", int_ppc_altivec_vminuh, v8i16>;
|
||||
def VMINUW : VX1_Int_Ty< 642, "vminuw", int_ppc_altivec_vminuw, v4i32>;
|
||||
|
||||
def VMRGHB : VXForm_1< 12, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGHB : VXForm_1< 12, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrghb $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrghb_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VMRGHH : VXForm_1< 76, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGHH : VXForm_1< 76, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrghh $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrghh_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VMRGHW : VXForm_1<140, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGHW : VXForm_1<140, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrghw $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrghw_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VMRGLB : VXForm_1<268, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGLB : VXForm_1<268, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrglb $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrglb_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VMRGLH : VXForm_1<332, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGLH : VXForm_1<332, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrglh $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrglh_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VMRGLW : VXForm_1<396, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VMRGLW : VXForm_1<396, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vmrglw $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD, (vmrglw_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
|
||||
@ -493,16 +493,16 @@ def VRSQRTEFP : VX2_Int_SP<330, "vrsqrtefp", int_ppc_altivec_vrsqrtefp>;
|
||||
|
||||
def VSUBCUW : VX1_Int_Ty<1408, "vsubcuw", int_ppc_altivec_vsubcuw, v4i32>;
|
||||
|
||||
def VSUBFP : VXForm_1<74, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VSUBFP : VXForm_1<74, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vsubfp $vD, $vA, $vB", VecGeneral,
|
||||
[(set v4f32:$vD, (fsub v4f32:$vA, v4f32:$vB))]>;
|
||||
def VSUBUBM : VXForm_1<1024, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VSUBUBM : VXForm_1<1024, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vsububm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v16i8:$vD, (sub v16i8:$vA, v16i8:$vB))]>;
|
||||
def VSUBUHM : VXForm_1<1088, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VSUBUHM : VXForm_1<1088, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vsubuhm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v8i16:$vD, (sub v8i16:$vA, v8i16:$vB))]>;
|
||||
def VSUBUWM : VXForm_1<1152, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VSUBUWM : VXForm_1<1152, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vsubuwm $vD, $vA, $vB", VecGeneral,
|
||||
[(set v4i32:$vD, (sub v4i32:$vA, v4i32:$vB))]>;
|
||||
|
||||
@ -523,14 +523,14 @@ def VSUM4SHS: VX1_Int_Ty3<1608, "vsum4shs", int_ppc_altivec_vsum4shs,
|
||||
def VSUM4UBS: VX1_Int_Ty3<1544, "vsum4ubs", int_ppc_altivec_vsum4ubs,
|
||||
v4i32, v16i8, v4i32>;
|
||||
|
||||
def VNOR : VXForm_1<1284, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VNOR : VXForm_1<1284, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vnor $vD, $vA, $vB", VecFP,
|
||||
[(set v4i32:$vD, (vnot_ppc (or v4i32:$vA,
|
||||
v4i32:$vB)))]>;
|
||||
def VOR : VXForm_1<1156, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VOR : VXForm_1<1156, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vor $vD, $vA, $vB", VecFP,
|
||||
[(set v4i32:$vD, (or v4i32:$vA, v4i32:$vB))]>;
|
||||
def VXOR : VXForm_1<1220, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VXOR : VXForm_1<1220, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vxor $vD, $vA, $vB", VecFP,
|
||||
[(set v4i32:$vD, (xor v4i32:$vA, v4i32:$vB))]>;
|
||||
|
||||
@ -545,15 +545,15 @@ def VSLB : VX1_Int_Ty< 260, "vslb", int_ppc_altivec_vslb, v16i8>;
|
||||
def VSLH : VX1_Int_Ty< 324, "vslh", int_ppc_altivec_vslh, v8i16>;
|
||||
def VSLW : VX1_Int_Ty< 388, "vslw", int_ppc_altivec_vslw, v4i32>;
|
||||
|
||||
def VSPLTB : VXForm_1<524, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VSPLTB : VXForm_1<524, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vspltb $vD, $vB, $UIMM", VecPerm,
|
||||
[(set v16i8:$vD,
|
||||
(vspltb_shuffle:$UIMM v16i8:$vB, (undef)))]>;
|
||||
def VSPLTH : VXForm_1<588, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VSPLTH : VXForm_1<588, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vsplth $vD, $vB, $UIMM", VecPerm,
|
||||
[(set v16i8:$vD,
|
||||
(vsplth_shuffle:$UIMM v16i8:$vB, (undef)))]>;
|
||||
def VSPLTW : VXForm_1<652, (outs VRRC:$vD), (ins u5imm:$UIMM, VRRC:$vB),
|
||||
def VSPLTW : VXForm_1<652, (outs vrrc:$vD), (ins u5imm:$UIMM, vrrc:$vB),
|
||||
"vspltw $vD, $vB, $UIMM", VecPerm,
|
||||
[(set v16i8:$vD,
|
||||
(vspltw_shuffle:$UIMM v16i8:$vB, (undef)))]>;
|
||||
@ -569,13 +569,13 @@ def VSRH : VX1_Int_Ty< 580, "vsrh" , int_ppc_altivec_vsrh , v8i16>;
|
||||
def VSRW : VX1_Int_Ty< 644, "vsrw" , int_ppc_altivec_vsrw , v4i32>;
|
||||
|
||||
|
||||
def VSPLTISB : VXForm_3<780, (outs VRRC:$vD), (ins s5imm:$SIMM),
|
||||
def VSPLTISB : VXForm_3<780, (outs vrrc:$vD), (ins s5imm:$SIMM),
|
||||
"vspltisb $vD, $SIMM", VecPerm,
|
||||
[(set v16i8:$vD, (v16i8 vecspltisb:$SIMM))]>;
|
||||
def VSPLTISH : VXForm_3<844, (outs VRRC:$vD), (ins s5imm:$SIMM),
|
||||
def VSPLTISH : VXForm_3<844, (outs vrrc:$vD), (ins s5imm:$SIMM),
|
||||
"vspltish $vD, $SIMM", VecPerm,
|
||||
[(set v8i16:$vD, (v8i16 vecspltish:$SIMM))]>;
|
||||
def VSPLTISW : VXForm_3<908, (outs VRRC:$vD), (ins s5imm:$SIMM),
|
||||
def VSPLTISW : VXForm_3<908, (outs vrrc:$vD), (ins s5imm:$SIMM),
|
||||
"vspltisw $vD, $SIMM", VecPerm,
|
||||
[(set v4i32:$vD, (v4i32 vecspltisw:$SIMM))]>;
|
||||
|
||||
@ -590,13 +590,13 @@ def VPKSWSS : VX1_Int_Ty2<462, "vpkswss", int_ppc_altivec_vpkswss,
|
||||
v16i8, v4i32>;
|
||||
def VPKSWUS : VX1_Int_Ty2<334, "vpkswus", int_ppc_altivec_vpkswus,
|
||||
v8i16, v4i32>;
|
||||
def VPKUHUM : VXForm_1<14, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VPKUHUM : VXForm_1<14, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vpkuhum $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD,
|
||||
(vpkuhum_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
def VPKUHUS : VX1_Int_Ty2<142, "vpkuhus", int_ppc_altivec_vpkuhus,
|
||||
v16i8, v8i16>;
|
||||
def VPKUWUM : VXForm_1<78, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),
|
||||
def VPKUWUM : VXForm_1<78, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
|
||||
"vpkuwum $vD, $vA, $vB", VecFP,
|
||||
[(set v16i8:$vD,
|
||||
(vpkuwum_shuffle v16i8:$vA, v16i8:$vB))]>;
|
||||
@ -621,10 +621,10 @@ def VUPKLSH : VX2_Int_Ty2<718, "vupklsh", int_ppc_altivec_vupklsh,
|
||||
// Altivec Comparisons.
|
||||
|
||||
class VCMP<bits<10> xo, string asmstr, ValueType Ty>
|
||||
: VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
|
||||
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare,
|
||||
[(set Ty:$vD, (Ty (PPCvcmp Ty:$vA, Ty:$vB, xo)))]>;
|
||||
class VCMPo<bits<10> xo, string asmstr, ValueType Ty>
|
||||
: VXRForm_1<xo, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vB),asmstr,VecFPCompare,
|
||||
: VXRForm_1<xo, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),asmstr,VecFPCompare,
|
||||
[(set Ty:$vD, (Ty (PPCvcmp_o Ty:$vA, Ty:$vB, xo)))]> {
|
||||
let Defs = [CR6];
|
||||
let RC = 1;
|
||||
@ -665,11 +665,11 @@ def VCMPGTUW : VCMP <646, "vcmpgtuw $vD, $vA, $vB" , v4i32>;
|
||||
def VCMPGTUWo : VCMPo<646, "vcmpgtuw. $vD, $vA, $vB", v4i32>;
|
||||
|
||||
let isCodeGenOnly = 1 in
|
||||
def V_SET0 : VXForm_setzero<1220, (outs VRRC:$vD), (ins),
|
||||
def V_SET0 : VXForm_setzero<1220, (outs vrrc:$vD), (ins),
|
||||
"vxor $vD, $vD, $vD", VecFP,
|
||||
[(set v4i32:$vD, (v4i32 immAllZerosV))]>;
|
||||
let IMM=-1 in {
|
||||
def V_SETALLONES : VXForm_3<908, (outs VRRC:$vD), (ins),
|
||||
def V_SETALLONES : VXForm_3<908, (outs vrrc:$vD), (ins),
|
||||
"vspltisw $vD, -1", VecFP,
|
||||
[(set v4i32:$vD, (v4i32 immAllOnesV))]>;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user