6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-11 11:34:02 +00:00
Code Issues Projects Releases Wiki Activity

ARM::MOVi32imm is expanded in ARMExpandPseudoInsts, so there's no need to

Browse Source 
handle it in the asm lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117707 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2010-10-29 20:37:06 +00:00
parent 9ae33fe396
commit a3c1629ff5
1 changed files with 0 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

55
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -949,61 +949,6 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
} }
return; return;
} }
case ARM::MOVi32imm: {
// FIXME: We'd like to remove the asm string in the .td file, but the
// This is a hack that lowers as a two instruction sequence.
unsigned DstReg = MI->getOperand(0).getReg();
const MachineOperand &MO = MI->getOperand(1);
MCOperand V1, V2;
if (MO.isImm()) {
unsigned ImmVal = (unsigned)MI->getOperand(1).getImm();
V1 = MCOperand::CreateImm(ImmVal & 65535);
V2 = MCOperand::CreateImm(ImmVal >> 16);
} else if (MO.isGlobal()) {
MCSymbol *Symbol = MCInstLowering.GetGlobalAddressSymbol(MO.getGlobal());
const MCSymbolRefExpr *SymRef1 =
MCSymbolRefExpr::Create(Symbol,
MCSymbolRefExpr::VK_ARM_LO16, OutContext);
const MCSymbolRefExpr *SymRef2 =
MCSymbolRefExpr::Create(Symbol,
MCSymbolRefExpr::VK_ARM_HI16, OutContext);
V1 = MCOperand::CreateExpr(SymRef1);
V2 = MCOperand::CreateExpr(SymRef2);
} else {
// FIXME: External symbol?
MI->dump();
llvm_unreachable("cannot handle this operand");
}
{
MCInst TmpInst;
TmpInst.setOpcode(ARM::MOVi16);
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
TmpInst.addOperand(V1); // lower16(imm)
// Predicate.
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
OutStreamer.EmitInstruction(TmpInst);
}
{
MCInst TmpInst;
TmpInst.setOpcode(ARM::MOVTi16);
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // dstreg
TmpInst.addOperand(MCOperand::CreateReg(DstReg)); // srcreg
TmpInst.addOperand(V2); // upper16(imm)
// Predicate.
TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(3).getReg()));
OutStreamer.EmitInstruction(TmpInst);
}
return;
}
case ARM::t2TBB: case ARM::t2TBB:
case ARM::t2TBH: case ARM::t2TBH:
case ARM::t2BR_JT: { case ARM::t2BR_JT: {