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[x86] Fix 16-bit disassembly of JCXZ/JECXZ

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199653 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Woodhouse 2014-01-20 12:02:48 +00:00
parent fc19ac9654
commit a3fb0f9773
2 changed files with 21 additions and 2 deletions
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19
lib/Target/X86/Disassembler/X86DisassemblerDecoder.c
View File

@ -987,6 +987,25 @@ static int getID(struct InternalInstruction* insn, const void *miiArg) {
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
/*
* JCXZ/JECXZ need special handling for 16-bit mode because the meaning
* of the AdSize prefix is inverted w.r.t. 32-bit mode.
*/
if (insn->mode == MODE_16BIT && insn->opcode == 0xE3) {
const struct InstructionSpecifier *spec;
spec = specifierForUID(instructionID);
/*
* Check for Ii8PCRel instructions. We could alternatively do a
* string-compare on the names, but this is probably cheaper.
*/
if (x86OperandSets[spec->operands][0].type == TYPE_REL8) {
attrMask ^= ATTR_ADSIZE;
if (getIDWithAttrMask(&instructionID, insn, attrMask))
return -1;
}
}
/* The following clauses compensate for limitations of the tables. */
if ((insn->mode == MODE_16BIT || insn->prefixPresent[0x66]) &&

4
test/MC/Disassembler/X86/x86-16.txt
View File

@ -297,10 +297,10 @@
# CHECK: lcalll $2, $4660
0x66 0x9a 0x34 0x12 0x00 0x00 0x02 0x00
# CHECKX: jcxz
# CHECK: jcxz
0xe3 0x00
# CHECKX: jecxz
# CHECK: jecxz
0x67 0xe3 0x00
# CHECK: iretw