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Initialize RegLimit only when register pressure is being tracked.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109079 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2010-07-22 05:18:41 +00:00
parent 9a9d275dc7
commit a4081238aa
1 changed files with 25 additions and 27 deletions
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52
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
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@@ -1036,7 +1036,7 @@ namespace {
std::vector<SUnit*> Queue; std::vector<SUnit*> Queue;
SF Picker; SF Picker;
unsigned CurQueueId; unsigned CurQueueId;
bool isBottomUp; bool TracksRegPressure;
protected: protected:
// SUnits - The SUnits for the current graph. // SUnits - The SUnits for the current graph.
@@ -1061,20 +1061,22 @@ namespace {
public: public:
RegReductionPriorityQueue(MachineFunction &mf, RegReductionPriorityQueue(MachineFunction &mf,
bool isbottomup, bool tracksrp,
const TargetInstrInfo *tii, const TargetInstrInfo *tii,
const TargetRegisterInfo *tri, const TargetRegisterInfo *tri,
const TargetLowering *tli) const TargetLowering *tli)
: Picker(this), CurQueueId(0), isBottomUp(isbottomup), : Picker(this), CurQueueId(0), TracksRegPressure(tracksrp),
MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) { MF(mf), TII(tii), TRI(tri), TLI(tli), scheduleDAG(NULL) {
unsigned NumRC = TRI->getNumRegClasses(); if (TracksRegPressure) {
RegLimit.resize(NumRC); unsigned NumRC = TRI->getNumRegClasses();
RegPressure.resize(NumRC); RegLimit.resize(NumRC);
std::fill(RegLimit.begin(), RegLimit.end(), 0); RegPressure.resize(NumRC);
std::fill(RegPressure.begin(), RegPressure.end(), 0); std::fill(RegLimit.begin(), RegLimit.end(), 0);
for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), std::fill(RegPressure.begin(), RegPressure.end(), 0);
E = TRI->regclass_end(); I != E; ++I) for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1; E = TRI->regclass_end(); I != E; ++I)
RegLimit[(*I)->getID()] = tri->getAllocatableSet(MF, *I).count() - 1;
}
} }
void initNodes(std::vector<SUnit> &sunits) { void initNodes(std::vector<SUnit> &sunits) {
@@ -1207,7 +1209,10 @@ namespace {
return false; return false;
} }
void OpenPredLives(SUnit *SU) { void ScheduledNode(SUnit *SU) {
if (!TracksRegPressure)
return;
const SDNode *N = SU->getNode(); const SDNode *N = SU->getNode();
if (!N->isMachineOpcode()) if (!N->isMachineOpcode())
return; return;
@@ -1260,9 +1265,14 @@ namespace {
else else
RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT); RegPressure[RCId] -= TLI->getRepRegClassCostFor(VT);
} }
dumpRegPressure();
} }
void ClosePredLives(SUnit *SU) { void UnscheduledNode(SUnit *SU) {
if (!TracksRegPressure)
return;
const SDNode *N = SU->getNode(); const SDNode *N = SU->getNode();
if (!N->isMachineOpcode()) if (!N->isMachineOpcode())
return; return;
@@ -1317,19 +1327,7 @@ namespace {
unsigned RCId = TLI->getRepRegClassFor(VT)->getID(); unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
RegPressure[RCId] += TLI->getRepRegClassCostFor(VT); RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
} }
}
void ScheduledNode(SUnit *SU) {
if (!TLI || !isBottomUp)
return;
OpenPredLives(SU);
dumpRegPressure();
}
void UnscheduledNode(SUnit *SU) {
if (!TLI || !isBottomUp)
return;
ClosePredLives(SU);
dumpRegPressure(); dumpRegPressure();
} }
@@ -1851,7 +1849,7 @@ llvm::createBURRListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
BURegReductionPriorityQueue *PQ = BURegReductionPriorityQueue *PQ =
new BURegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0); new BURegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ); ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD); PQ->setScheduleDAG(SD);
return SD; return SD;
@@ -1877,7 +1875,7 @@ llvm::createSourceListDAGScheduler(SelectionDAGISel *IS, CodeGenOpt::Level) {
const TargetRegisterInfo *TRI = TM.getRegisterInfo(); const TargetRegisterInfo *TRI = TM.getRegisterInfo();
SrcRegReductionPriorityQueue *PQ = SrcRegReductionPriorityQueue *PQ =
new SrcRegReductionPriorityQueue(*IS->MF, true, TII, TRI, 0); new SrcRegReductionPriorityQueue(*IS->MF, false, TII, TRI, 0);
ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ); ScheduleDAGRRList *SD = new ScheduleDAGRRList(*IS->MF, true, false, PQ);
PQ->setScheduleDAG(SD); PQ->setScheduleDAG(SD);
return SD; return SD;