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https://github.com/c64scene-ar/llvm-6502.git
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R600/SI: Improve legalization of vector operations
This should fix hangs in the OpenCL piglit tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188431 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
parent
e8e33f448e
commit
a41520cf9b
@ -79,8 +79,10 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::LOAD, MVT::f64, Promote);
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AddPromotedToType(ISD::LOAD, MVT::f64, MVT::i64);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Expand);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Expand);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom);
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setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2i32, Custom);
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setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v2f32, Custom);
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setOperationAction(ISD::FNEG, MVT::v2f32, Expand);
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setOperationAction(ISD::FNEG, MVT::v4f32, Expand);
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@ -182,6 +184,8 @@ SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
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case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
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case ISD::BRCOND: return LowerBRCOND(Op, DAG);
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// AMDGPU DAG lowering
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case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG);
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case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG);
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case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
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case ISD::UDIVREM: return LowerUDIVREM(Op, DAG);
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}
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@ -208,6 +212,47 @@ SDValue AMDGPUTargetLowering::LowerGlobalAddress(AMDGPUMachineFunction* MFI,
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return DAG.getConstant(Offset, TD->getPointerSize() == 8 ? MVT::i64 : MVT::i32);
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}
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void AMDGPUTargetLowering::ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Args,
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unsigned Start,
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unsigned Count) const {
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EVT VT = Op.getValueType();
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for (unsigned i = Start, e = Start + Count; i != e; ++i) {
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Args.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
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VT.getVectorElementType(),
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Op, DAG.getConstant(i, MVT::i32)));
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}
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}
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SDValue AMDGPUTargetLowering::LowerCONCAT_VECTORS(SDValue Op,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Args;
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SDValue A = Op.getOperand(0);
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SDValue B = Op.getOperand(1);
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ExtractVectorElements(A, DAG, Args, 0,
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A.getValueType().getVectorNumElements());
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ExtractVectorElements(B, DAG, Args, 0,
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B.getValueType().getVectorNumElements());
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
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&Args[0], Args.size());
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}
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SDValue AMDGPUTargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op,
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SelectionDAG &DAG) const {
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SmallVector<SDValue, 8> Args;
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EVT VT = Op.getValueType();
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unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
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ExtractVectorElements(Op.getOperand(0), DAG, Args, Start,
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VT.getVectorNumElements());
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(Op), Op.getValueType(),
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&Args[0], Args.size());
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}
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SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
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SelectionDAG &DAG) const {
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unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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@ -25,6 +25,11 @@ class MachineRegisterInfo;
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class AMDGPUTargetLowering : public TargetLowering {
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private:
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void ExtractVectorElements(SDValue Op, SelectionDAG &DAG,
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SmallVectorImpl<SDValue> &Args,
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unsigned Start, unsigned Count) const;
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SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
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SDValue LowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
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@ -34,9 +34,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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addRegisterClass(MVT::i1, &AMDGPU::SReg_64RegClass);
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addRegisterClass(MVT::i64, &AMDGPU::VSrc_64RegClass);
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addRegisterClass(MVT::v2i1, &AMDGPU::VReg_64RegClass);
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addRegisterClass(MVT::v4i1, &AMDGPU::VReg_128RegClass);
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addRegisterClass(MVT::v32i8, &AMDGPU::SReg_256RegClass);
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addRegisterClass(MVT::v64i8, &AMDGPU::SReg_512RegClass);
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@ -110,6 +107,9 @@ bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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return VT.bitsGT(MVT::i32);
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}
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bool SITargetLowering::shouldSplitVectorElementType(EVT VT) const {
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return VT.bitsLE(MVT::i8);
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}
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SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT,
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SDLoc DL, SDValue Chain,
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@ -47,6 +47,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
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public:
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SITargetLowering(TargetMachine &tm);
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bool allowsUnalignedMemoryAccesses(EVT VT, bool *IsFast) const;
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virtual bool shouldSplitVectorElementType(EVT VT) const;
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SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
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bool isVarArg,
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111
test/CodeGen/R600/si-vector-hang.ll
Normal file
111
test/CodeGen/R600/si-vector-hang.ll
Normal file
@ -0,0 +1,111 @@
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; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck %s
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; XXX: Mark this test as XFAIL until buffer stores are implemented
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; XFAIL: *
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; CHECK: @test_8_min_char
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; CHECK: BUFFER_STORE_BYTE
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; ModuleID = 'radeon'
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048-n32:64"
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target triple = "r600--"
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; Function Attrs: nounwind
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define void @test_8_min_char(i8 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture readonly %in0, i8 addrspace(1)* nocapture readonly %in1) #0 {
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entry:
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%0 = load i8 addrspace(1)* %in0, align 1, !tbaa !9
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%1 = insertelement <8 x i8> undef, i8 %0, i32 0
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%arrayidx2.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 1
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%2 = load i8 addrspace(1)* %arrayidx2.i.i, align 1, !tbaa !9
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%3 = insertelement <8 x i8> %1, i8 %2, i32 1
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%arrayidx6.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 2
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%4 = load i8 addrspace(1)* %arrayidx6.i.i, align 1, !tbaa !9
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%5 = insertelement <8 x i8> %3, i8 %4, i32 2
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%arrayidx10.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 3
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%6 = load i8 addrspace(1)* %arrayidx10.i.i, align 1, !tbaa !9
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%7 = insertelement <8 x i8> %5, i8 %6, i32 3
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%arrayidx.i.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 4
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%8 = load i8 addrspace(1)* %arrayidx.i.i, align 1, !tbaa !9
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%9 = insertelement <8 x i8> undef, i8 %8, i32 0
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%arrayidx2.i9.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 5
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%10 = load i8 addrspace(1)* %arrayidx2.i9.i, align 1, !tbaa !9
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%11 = insertelement <8 x i8> %9, i8 %10, i32 1
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%arrayidx6.i11.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 6
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%12 = load i8 addrspace(1)* %arrayidx6.i11.i, align 1, !tbaa !9
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%13 = insertelement <8 x i8> %11, i8 %12, i32 2
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%arrayidx10.i13.i = getelementptr inbounds i8 addrspace(1)* %in0, i64 7
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%14 = load i8 addrspace(1)* %arrayidx10.i13.i, align 1, !tbaa !9
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%15 = insertelement <8 x i8> %13, i8 %14, i32 3
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%vecinit5.i = shufflevector <8 x i8> %7, <8 x i8> %15, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%16 = load i8 addrspace(1)* %in1, align 1, !tbaa !9
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%17 = insertelement <8 x i8> undef, i8 %16, i32 0
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%arrayidx2.i.i4 = getelementptr inbounds i8 addrspace(1)* %in1, i64 1
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%18 = load i8 addrspace(1)* %arrayidx2.i.i4, align 1, !tbaa !9
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%19 = insertelement <8 x i8> %17, i8 %18, i32 1
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%arrayidx6.i.i5 = getelementptr inbounds i8 addrspace(1)* %in1, i64 2
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%20 = load i8 addrspace(1)* %arrayidx6.i.i5, align 1, !tbaa !9
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%21 = insertelement <8 x i8> %19, i8 %20, i32 2
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%arrayidx10.i.i6 = getelementptr inbounds i8 addrspace(1)* %in1, i64 3
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%22 = load i8 addrspace(1)* %arrayidx10.i.i6, align 1, !tbaa !9
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%23 = insertelement <8 x i8> %21, i8 %22, i32 3
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%arrayidx.i.i7 = getelementptr inbounds i8 addrspace(1)* %in1, i64 4
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%24 = load i8 addrspace(1)* %arrayidx.i.i7, align 1, !tbaa !9
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%25 = insertelement <8 x i8> undef, i8 %24, i32 0
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%arrayidx2.i9.i8 = getelementptr inbounds i8 addrspace(1)* %in1, i64 5
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%26 = load i8 addrspace(1)* %arrayidx2.i9.i8, align 1, !tbaa !9
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%27 = insertelement <8 x i8> %25, i8 %26, i32 1
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%arrayidx6.i11.i9 = getelementptr inbounds i8 addrspace(1)* %in1, i64 6
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%28 = load i8 addrspace(1)* %arrayidx6.i11.i9, align 1, !tbaa !9
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%29 = insertelement <8 x i8> %27, i8 %28, i32 2
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%arrayidx10.i13.i10 = getelementptr inbounds i8 addrspace(1)* %in1, i64 7
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%30 = load i8 addrspace(1)* %arrayidx10.i13.i10, align 1, !tbaa !9
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%31 = insertelement <8 x i8> %29, i8 %30, i32 3
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%vecinit5.i11 = shufflevector <8 x i8> %23, <8 x i8> %31, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
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%cmp.i = icmp slt <8 x i8> %vecinit5.i, %vecinit5.i11
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%cond.i = select <8 x i1> %cmp.i, <8 x i8> %vecinit5.i, <8 x i8> %vecinit5.i11
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%32 = extractelement <8 x i8> %cond.i, i32 0
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store i8 %32, i8 addrspace(1)* %out, align 1, !tbaa !9
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%33 = extractelement <8 x i8> %cond.i, i32 1
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%arrayidx2.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 1
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store i8 %33, i8 addrspace(1)* %arrayidx2.i.i.i, align 1, !tbaa !9
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%34 = extractelement <8 x i8> %cond.i, i32 2
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%arrayidx.i.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 2
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store i8 %34, i8 addrspace(1)* %arrayidx.i.i.i, align 1, !tbaa !9
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%35 = extractelement <8 x i8> %cond.i, i32 3
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%arrayidx2.i6.i.i = getelementptr inbounds i8 addrspace(1)* %out, i64 3
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store i8 %35, i8 addrspace(1)* %arrayidx2.i6.i.i, align 1, !tbaa !9
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%arrayidx.i.i3 = getelementptr inbounds i8 addrspace(1)* %out, i64 4
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%36 = extractelement <8 x i8> %cond.i, i32 4
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store i8 %36, i8 addrspace(1)* %arrayidx.i.i3, align 1, !tbaa !9
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%37 = extractelement <8 x i8> %cond.i, i32 5
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%arrayidx2.i.i6.i = getelementptr inbounds i8 addrspace(1)* %out, i64 5
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store i8 %37, i8 addrspace(1)* %arrayidx2.i.i6.i, align 1, !tbaa !9
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%38 = extractelement <8 x i8> %cond.i, i32 6
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%arrayidx.i.i7.i = getelementptr inbounds i8 addrspace(1)* %out, i64 6
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store i8 %38, i8 addrspace(1)* %arrayidx.i.i7.i, align 1, !tbaa !9
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%39 = extractelement <8 x i8> %cond.i, i32 7
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%arrayidx2.i6.i8.i = getelementptr inbounds i8 addrspace(1)* %out, i64 7
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store i8 %39, i8 addrspace(1)* %arrayidx2.i6.i8.i, align 1, !tbaa !9
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ret void
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}
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-frame-pointer-elim-non-leaf"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!opencl.kernels = !{!0, !1, !2, !3, !4, !5, !6, !7, !8}
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!0 = metadata !{null}
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!1 = metadata !{null}
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!2 = metadata !{null}
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!3 = metadata !{void (i8 addrspace(1)*, i8 addrspace(1)*, i8 addrspace(1)*)* @test_8_min_char}
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!4 = metadata !{null}
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!5 = metadata !{null}
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!6 = metadata !{null}
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!7 = metadata !{null}
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!8 = metadata !{null}
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!9 = metadata !{metadata !"omnipotent char", metadata !10}
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!10 = metadata !{metadata !"Simple C/C++ TBAA"}
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