6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 00:17:01 +00:00
Code Issues Projects Releases Wiki Activity

Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83502 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bob Wilson
2009-10-07 22:57:01 +00:00
parent 9f3a559dff
commit a4288080e6
4 changed files with 17 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/ARM/ARMISelDAGToDAG.cpp
View File

@@ -1357,6 +1357,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
case MVT::v4i16: Opc = ARM::VLD2d16; break;
case MVT::v2f32:
case MVT::v2i32: Opc = ARM::VLD2d32; break;
case MVT::v1i64: Opc = ARM::VLD2d64; break;
}
SDValue Chain = N->getOperand(0);
const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };

3
lib/Target/ARM/ARMInstrNEON.td
View File

@@ -193,6 +193,9 @@ class VLD2Q<bits<4> op7_4, string OpcodeStr>
def VLD2d8 : VLD2D<0b0000, "vld2.8">;
def VLD2d16 : VLD2D<0b0100, "vld2.16">;
def VLD2d32 : VLD2D<0b1000, "vld2.32">;
def VLD2d64 : NLdSt<0,0b10,0b1010,0b1100, (outs DPR:$dst1, DPR:$dst2),
(ins addrmode6:$addr), IIC_VLD1,
"vld1.64\t\\{$dst1,$dst2\\}, $addr", "", []>;
def VLD2q8 : VLD2Q<0b0000, "vld2.8">;
def VLD2q16 : VLD2Q<0b0100, "vld2.16">;

1
lib/Target/ARM/NEONPreAllocPass.cpp
View File

@@ -49,6 +49,7 @@ static bool isNEONMultiRegOp(int Opcode, unsigned &FirstOpnd, unsigned &NumRegs,
case ARM::VLD2d8:
case ARM::VLD2d16:
case ARM::VLD2d32:
case ARM::VLD2d64:
case ARM::VLD2LNd8:
case ARM::VLD2LNd16:
case ARM::VLD2LNd32: