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[Sparc] Clean up branch instructions, so that TableGen can encode branch conditions as well. No functionality change intended.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Venkatraman Govindaraju 2013-09-22 08:51:55 +00:00
parent 3e84ad28d4
commit a432a97b62
3 changed files with 26 additions and 23 deletions
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6
lib/Target/Sparc/SparcInstr64Bit.td
View File

@ -321,9 +321,9 @@ def : Pat<(store (i64 0), ADDRri:$dst), (STXri ADDRri:$dst, (i64 G0))>;
let Predicates = [Is64Bit] in {
let Uses = [ICC] in
def BPXCC : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
"b$cc %xcc, $dst",
[(SPbrxcc bb:$dst, imm:$cc)]>;
def BPXCC : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
"b$cond %xcc, $imm22",
[(SPbrxcc bb:$imm22, imm:$cond)]>;
// Conditional moves on %xcc.
let Uses = [ICC], Constraints = "$f = $rd" in {

3
lib/Target/Sparc/SparcInstrFormats.td
View File

@ -47,12 +47,11 @@ class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{29-25} = rd;
}
class F2_2<bits<4> condVal, bits<3> op2Val, dag outs, dag ins, string asmstr,
class F2_2<bits<3> op2Val, dag outs, dag ins, string asmstr,
list<dag> pattern> : F2<outs, ins, asmstr, pattern> {
bits<4> cond;
bit annul = 0; // currently unused
let cond = condVal;
let op2 = op2Val;
let Inst{29} = annul;

40
lib/Target/Sparc/SparcInstrInfo.td
View File

@ -548,19 +548,26 @@ defm RESTORE : F3_12np<"restore", 0b111101>;
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// unconditional branch class.
class BranchAlways<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b010, (outs), ins, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
let isBarrier = 1;
}
let cond = 8 in
def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
// conditional branch class:
class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
: F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
class BranchSP<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b010, (outs), ins, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
}
let isBarrier = 1 in
def BA : BranchSP<0b1000, (ins brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
// Indirect branch instructions.
let isTerminator = 1, isBarrier = 1,
hasDelaySlot = 1, isBranch =1,
@ -575,28 +582,25 @@ let isTerminator = 1, isBarrier = 1,
[(brind ADDRri:$ptr)]>;
}
// FIXME: the encoding for the JIT should look at the condition field.
let Uses = [ICC] in
def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
"b$cc $dst",
[(SPbricc bb:$dst, imm:$cc)]>;
def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
"b$cond $imm22",
[(SPbricc bb:$imm22, imm:$cond)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
: F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
: F2_2<0b110, (outs), ins, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 1;
}
// FIXME: the encoding for the JIT should look at the condition field.
let Uses = [FCC] in
def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
"fb$cc $dst",
[(SPbrfcc bb:$dst, imm:$cc)]>;
def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
"fb$cond $imm22",
[(SPbrfcc bb:$imm22, imm:$cond)]>;
// Section B.24 - Call and Link Instruction, p. 125