From a45e3747e612c00ca4933087d883db77f4547571 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Fri, 30 Mar 2012 18:53:01 +0000 Subject: [PATCH] ARM encoding for VSWP got the second operand incorrect. Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrNEON.td | 8 ++++---- test/MC/ARM/neon-vswp.s | 7 +++++++ 2 files changed, 11 insertions(+), 4 deletions(-) create mode 100644 test/MC/ARM/neon-vswp.s diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index c5458ed4d04..dc5298c2d94 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -4787,12 +4787,12 @@ def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0, // Vector Swap def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0, - (outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1), - NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1", + (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2), + NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", []>; def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0, - (outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1), - NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1", + (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2), + NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm", []>; // Vector Move Operations. diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s new file mode 100644 index 00000000000..2138eedf4c2 --- /dev/null +++ b/test/MC/ARM/neon-vswp.s @@ -0,0 +1,7 @@ +@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s + +vswp d1, d2 +vswp q1, q2 + +@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3] +@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]