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https://github.com/c64scene-ar/llvm-6502.git
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[ARM64] Shifted register ALU ops are reserved if sf=0 and imm6<5>=1, and also (for add/sub only) if shift=11.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205865 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith
parent
a5b549e03c
commit
a493b7786a
@ -854,6 +854,14 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
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switch (Inst.getOpcode()) {
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default:
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return Fail;
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case ARM64::ADDWrs:
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case ARM64::ADDSWrs:
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case ARM64::SUBWrs:
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case ARM64::SUBSWrs:
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// if shift == '11' then ReservedValue()
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if (shiftHi == 0x3)
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return Fail;
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// Deliberate fallthrough
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case ARM64::ANDWrs:
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case ARM64::ANDSWrs:
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case ARM64::BICWrs:
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@ -861,16 +869,23 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
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case ARM64::ORRWrs:
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case ARM64::ORNWrs:
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case ARM64::EORWrs:
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case ARM64::EONWrs:
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case ARM64::ADDWrs:
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case ARM64::ADDSWrs:
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case ARM64::SUBWrs:
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case ARM64::SUBSWrs: {
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case ARM64::EONWrs: {
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// if sf == '0' and imm6<5> == '1' then ReservedValue()
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if (shiftLo >> 5 == 1)
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return Fail;
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DecodeGPR32RegisterClass(Inst, Rd, Addr, Decoder);
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DecodeGPR32RegisterClass(Inst, Rn, Addr, Decoder);
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DecodeGPR32RegisterClass(Inst, Rm, Addr, Decoder);
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break;
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}
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case ARM64::ADDXrs:
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case ARM64::ADDSXrs:
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case ARM64::SUBXrs:
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case ARM64::SUBSXrs:
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// if shift == '11' then ReservedValue()
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if (shiftHi == 0x3)
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return Fail;
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// Deliberate fallthrough
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case ARM64::ANDXrs:
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case ARM64::ANDSXrs:
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case ARM64::BICXrs:
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@ -879,10 +894,6 @@ static DecodeStatus DecodeThreeAddrSRegInstruction(llvm::MCInst &Inst,
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case ARM64::ORNXrs:
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case ARM64::EORXrs:
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case ARM64::EONXrs:
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case ARM64::ADDXrs:
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case ARM64::ADDSXrs:
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case ARM64::SUBXrs:
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case ARM64::SUBSXrs:
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DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
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DecodeGPR64RegisterClass(Inst, Rn, Addr, Decoder);
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DecodeGPR64RegisterClass(Inst, Rm, Addr, Decoder);
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@ -85,72 +85,72 @@
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0xac 0x01 0x0e 0x8b
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0xac 0x31 0x0e 0x0b
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0xac 0x31 0x0e 0x8b
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0xac 0xa9 0x4e 0x0b
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0xac 0xa9 0x4e 0x8b
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0xac 0x9d 0x8e 0x0b
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0xac 0x29 0x4e 0x0b
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0xac 0x29 0x4e 0x8b
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0xac 0x1d 0x8e 0x0b
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0xac 0x9d 0x8e 0x8b
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# CHECK: add w12, w13, w14
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# CHECK: add x12, x13, x14
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# CHECK: add w12, w13, w14, lsl #12
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# CHECK: add x12, x13, x14, lsl #12
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# CHECK: add w12, w13, w14, lsr #42
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# CHECK: add x12, x13, x14, lsr #42
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# CHECK: add w12, w13, w14, asr #39
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# CHECK: add w12, w13, w14, lsr #10
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# CHECK: add x12, x13, x14, lsr #10
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# CHECK: add w12, w13, w14, asr #7
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# CHECK: add x12, x13, x14, asr #39
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0xac 0x01 0x0e 0x4b
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0xac 0x01 0x0e 0xcb
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0xac 0x31 0x0e 0x4b
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0xac 0x31 0x0e 0xcb
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0xac 0xa9 0x4e 0x4b
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0xac 0xa9 0x4e 0xcb
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0xac 0x9d 0x8e 0x4b
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0xac 0x29 0x4e 0x4b
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0xac 0x29 0x4e 0xcb
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0xac 0x1d 0x8e 0x4b
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0xac 0x9d 0x8e 0xcb
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# CHECK: sub w12, w13, w14
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# CHECK: sub x12, x13, x14
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# CHECK: sub w12, w13, w14, lsl #12
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# CHECK: sub x12, x13, x14, lsl #12
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# CHECK: sub w12, w13, w14, lsr #42
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# CHECK: sub x12, x13, x14, lsr #42
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# CHECK: sub w12, w13, w14, asr #39
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# CHECK: sub w12, w13, w14, lsr #10
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# CHECK: sub x12, x13, x14, lsr #10
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# CHECK: sub w12, w13, w14, asr #7
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# CHECK: sub x12, x13, x14, asr #39
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0xac 0x01 0x0e 0x2b
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0xac 0x01 0x0e 0xab
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0xac 0x31 0x0e 0x2b
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0xac 0x31 0x0e 0xab
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0xac 0xa9 0x4e 0x2b
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0xac 0xa9 0x4e 0xab
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0xac 0x9d 0x8e 0x2b
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0xac 0x29 0x4e 0x2b
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0xac 0x29 0x4e 0xab
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0xac 0x1d 0x8e 0x2b
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0xac 0x9d 0x8e 0xab
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# CHECK: adds w12, w13, w14
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# CHECK: adds x12, x13, x14
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# CHECK: adds w12, w13, w14, lsl #12
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# CHECK: adds x12, x13, x14, lsl #12
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# CHECK: adds w12, w13, w14, lsr #42
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# CHECK: adds x12, x13, x14, lsr #42
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# CHECK: adds w12, w13, w14, asr #39
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# CHECK: adds w12, w13, w14, lsr #10
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# CHECK: adds x12, x13, x14, lsr #10
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# CHECK: adds w12, w13, w14, asr #7
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# CHECK: adds x12, x13, x14, asr #39
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0xac 0x01 0x0e 0x6b
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0xac 0x01 0x0e 0xeb
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0xac 0x31 0x0e 0x6b
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0xac 0x31 0x0e 0xeb
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0xac 0xa9 0x4e 0x6b
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0xac 0xa9 0x4e 0xeb
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0xac 0x9d 0x8e 0x6b
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0xac 0x29 0x4e 0x6b
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0xac 0x29 0x4e 0xeb
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0xac 0x1d 0x8e 0x6b
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0xac 0x9d 0x8e 0xeb
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# CHECK: subs w12, w13, w14
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# CHECK: subs x12, x13, x14
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# CHECK: subs w12, w13, w14, lsl #12
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# CHECK: subs x12, x13, x14, lsl #12
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# CHECK: subs w12, w13, w14, lsr #42
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# CHECK: subs x12, x13, x14, lsr #42
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# CHECK: subs w12, w13, w14, asr #39
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# CHECK: subs w12, w13, w14, lsr #10
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# CHECK: subs x12, x13, x14, lsr #10
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# CHECK: subs w12, w13, w14, asr #7
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# CHECK: subs x12, x13, x14, asr #39
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#==---------------------------------------------------------------------------==
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@ -13,4 +13,9 @@
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# MOVK with sf == 0 and hw<1> == 1 is unallocated.
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# RUN: echo "0x00 0x00 0xc0 0x72" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# ADD/SUB (shifted register) are reserved if shift == '11' or sf == '0' and imm6<5> == '1'.
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# RUN: echo "0x00 0x00 0xc0 0xeb" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# RUN: echo "0x00 0x80 0x80 0x6b" | llvm-mc -triple=arm64 -disassemble 2>&1 | FileCheck %s
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# CHECK: invalid instruction encoding
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