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AMDGPU/SI: Simplify moveSMRDToVALU()

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Summary:
Replace the switch on instruction opcode with a switch on register size.
This way we don't need to update the switch statement when we add new
SMRD variants.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11601

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@243652 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard committed 2015-07-30 16:20:42 +00:00
1 parent a3a8dc4c30
commit a495784ea0
1 file changed
+9 -11
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lib/Target/AMDGPU/SIInstrInfo.cpp
+9 -11
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@@ -2056,13 +2056,13 @@ void SIInstrInfo::splitSMRD(MachineInstr *MI,
void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const { void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) const {
MachineBasicBlock *MBB = MI->getParent(); MachineBasicBlock *MBB = MI->getParent();
switch (MI->getOpcode()) { int DstIdx = AMDGPU::getNamedOperandIdx(MI->getOpcode(), AMDGPU::OpName::dst);
case AMDGPU::S_LOAD_DWORD_IMM: assert(DstIdx != -1);
case AMDGPU::S_LOAD_DWORD_SGPR: unsigned DstRCID = get(MI->getOpcode()).OpInfo[DstIdx].RegClass;
case AMDGPU::S_LOAD_DWORDX2_IMM: switch(RI.getRegClass(DstRCID)->getSize()) {
case AMDGPU::S_LOAD_DWORDX2_SGPR: case 4:
case AMDGPU::S_LOAD_DWORDX4_IMM: case 8:
case AMDGPU::S_LOAD_DWORDX4_SGPR: { case 16: {
unsigned NewOpcode = getVALUOp(*MI); unsigned NewOpcode = getVALUOp(*MI);
unsigned RegOffset; unsigned RegOffset;
unsigned ImmOffset; unsigned ImmOffset;
@@ -2134,8 +2134,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
MRI.replaceRegWith(DstReg, NewDstReg); MRI.replaceRegWith(DstReg, NewDstReg);
break; break;
} }
case AMDGPU::S_LOAD_DWORDX8_IMM: case 32: {
case AMDGPU::S_LOAD_DWORDX8_SGPR: {
MachineInstr *Lo, *Hi; MachineInstr *Lo, *Hi;
splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM, splitSMRD(MI, &AMDGPU::SReg_128RegClass, AMDGPU::S_LOAD_DWORDX4_IMM,
AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi); AMDGPU::S_LOAD_DWORDX4_SGPR, Lo, Hi);
@@ -2145,8 +2144,7 @@ void SIInstrInfo::moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI) con
break; break;
} }
case AMDGPU::S_LOAD_DWORDX16_IMM: case 64: {
case AMDGPU::S_LOAD_DWORDX16_SGPR: {
MachineInstr *Lo, *Hi; MachineInstr *Lo, *Hi;
splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM, splitSMRD(MI, &AMDGPU::SReg_256RegClass, AMDGPU::S_LOAD_DWORDX8_IMM,
AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi); AMDGPU::S_LOAD_DWORDX8_SGPR, Lo, Hi);