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Don't add implicit regs

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4840 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2002-12-01 23:24:58 +00:00
parent c2505985ce
commit a4978ccbcb
2 changed files with 2 additions and 2 deletions
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2
lib/Target/X86/InstSelectSimple.cpp
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@@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
if (isSigned) { if (isSigned) {
// Emit a sign extension instruction... // Emit a sign extension instruction...
BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); BuildMI(BB, ExtOpcode[Class], 0);
} else { } else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg) // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);

2
lib/Target/X86/X86ISelSimple.cpp
View File

@@ -502,7 +502,7 @@ void ISel::visitDivRem(BinaryOperator &I) {
if (isSigned) { if (isSigned) {
// Emit a sign extension instruction... // Emit a sign extension instruction...
BuildMI(BB, ExtOpcode[Class], 1, ExtReg).addReg(Reg); BuildMI(BB, ExtOpcode[Class], 0);
} else { } else {
// If unsigned, emit a zeroing instruction... (reg = xor reg, reg) // If unsigned, emit a zeroing instruction... (reg = xor reg, reg)
BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg);