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commuteInstr() can now commute non-ssa machine instrs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47043 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2008-02-13 02:46:49 +00:00
parent 1eb5cf9c7d
commit a4d16a1f0d
3 changed files with 28 additions and 0 deletions
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9
lib/CodeGen/TargetInstrInfoImpl.cpp
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@ -23,8 +23,17 @@ MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
"This only knows how to commute register operands so far"); "This only knows how to commute register operands so far");
unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg(); unsigned Reg2 = MI->getOperand(2).getReg();
MachineOperand &MO = MI->getOperand(0);
bool UpdateReg0 = MO.isReg() && MO.getReg() == Reg1;
bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill();
if (UpdateReg0) {
// Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!");
Reg2IsKill = false;
MI->getOperand(0).setReg(Reg2);
}
MI->getOperand(2).setReg(Reg1); MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2); MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill); MI->getOperand(2).setIsKill(Reg1IsKill);

10
lib/Target/PowerPC/PPCInstrInfo.cpp
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@ -147,10 +147,20 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
// Op0 = (Op2 & ~M) | (Op1 & M) // Op0 = (Op2 & ~M) | (Op1 & M)
// Swap op1/op2 // Swap op1/op2
unsigned Reg0 = MI->getOperand(0).getReg();
unsigned Reg1 = MI->getOperand(1).getReg(); unsigned Reg1 = MI->getOperand(1).getReg();
unsigned Reg2 = MI->getOperand(2).getReg(); unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill(); bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill(); bool Reg2IsKill = MI->getOperand(2).isKill();
// If machine instrs are no longer in two-address forms, update
// destination register as well.
if (Reg0 == Reg1) {
// Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!");
MI->getOperand(0).setReg(Reg2);
Reg2IsKill = false;
}
MI->getOperand(2).setReg(Reg1); MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2); MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill); MI->getOperand(2).setIsKill(Reg1IsKill);

9
lib/Target/X86/X86InstrInfo.cpp
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@ -1055,6 +1055,15 @@ MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
unsigned C = MI->getOperand(2).getReg(); unsigned C = MI->getOperand(2).getReg();
bool BisKill = MI->getOperand(1).isKill(); bool BisKill = MI->getOperand(1).isKill();
bool CisKill = MI->getOperand(2).isKill(); bool CisKill = MI->getOperand(2).isKill();
// If machine instrs are no longer in two-address forms, update
// destination register as well.
if (A == B) {
// Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!");
A = C;
CisKill = false;
}
return BuildMI(get(Opc), A).addReg(C, false, false, CisKill) return BuildMI(get(Opc), A).addReg(C, false, false, CisKill)
.addReg(B, false, false, BisKill).addImm(Size-Amt); .addReg(B, false, false, BisKill).addImm(Size-Amt);
} }