6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-02 07:17:36 +00:00
Code Issues Projects Releases Wiki Activity

[AVX512] Enabling MIN/MAX lowering.

Browse Source 
Added lowering tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@224127 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Khasanov
2014-12-12 15:10:43 +00:00
parent de48903a20
commit a4f5a5525d
6 changed files with 2830 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
lib/Target/X86/X86ISelLowering.cpp
View File

@@ -22606,6 +22606,21 @@ matchIntegerMINMAX(SDValue Cond, EVT VT, SDValue LHS, SDValue RHS,
bool NeedSplit = false;
switch (VT.getSimpleVT().SimpleTy) {
default: return std::make_pair(0, false);
case MVT::v4i64:
case MVT::v2i64:
if (!Subtarget->hasVLX())
return std::make_pair(0, false);
break;
case MVT::v64i8:
case MVT::v32i16:
if (!Subtarget->hasBWI())
return std::make_pair(0, false);
break;
case MVT::v16i32:
case MVT::v8i64:
if (!Subtarget->hasAVX512())
return std::make_pair(0, false);
break;
case MVT::v32i8:
case MVT::v16i16:
case MVT::v8i32:

8
lib/Target/X86/X86InstrSSE.td
View File

@@ -2852,7 +2852,7 @@ multiclass PDI_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
multiclass PDI_binop_all<bits<8> opc, string OpcodeStr, SDNode Opcode,
ValueType OpVT128, ValueType OpVT256,
OpndItins itins, bit IsCommutable = 0> {
let Predicates = [HasAVX] in
let Predicates = [HasAVX, NoVLX] in
defm V#NAME : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode, OpVT128,
VR128, loadv2i64, i128mem, itins, IsCommutable, 0>, VEX_4V;
@@ -2860,7 +2860,7 @@ let Constraints = "$src1 = $dst" in
defm NAME : PDI_binop_rm<opc, OpcodeStr, Opcode, OpVT128, VR128,
memopv2i64, i128mem, itins, IsCommutable, 1>;
let Predicates = [HasAVX2] in
let Predicates = [HasAVX2, NoVLX] in
defm V#NAME#Y : PDI_binop_rm<opc, !strconcat("v", OpcodeStr), Opcode,
OpVT256, VR256, loadv4i64, i256mem, itins,
IsCommutable, 0>, VEX_4V, VEX_L;
@@ -7100,7 +7100,7 @@ multiclass SS48I_binop_rm2<bits<8> opc, string OpcodeStr, SDNode OpNode,
Sched<[itins.Sched.Folded, ReadAfterLd]>;
}
let Predicates = [HasAVX] in {
let Predicates = [HasAVX, NoVLX] in {
let isCommutable = 0 in
defm VPMINSB : SS48I_binop_rm<0x38, "vpminsb", X86smin, v16i8, VR128,
loadv2i64, i128mem, 0, SSE_INTALU_ITINS_P>,
@@ -7131,7 +7131,7 @@ let Predicates = [HasAVX] in {
SSE_INTMUL_ITINS_P, 1, 0>, VEX_4V;
}
let Predicates = [HasAVX2] in {
let Predicates = [HasAVX2, NoVLX] in {
let isCommutable = 0 in
defm VPMINSBY : SS48I_binop_rm<0x38, "vpminsb", X86smin, v32i8, VR256,
loadv4i64, i256mem, 0, SSE_INTALU_ITINS_P>,