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SelectionDAG::SignBitIsZero doesn't work right for vectors,
for now, conservatively return false. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74969 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1516,6 +1516,10 @@ SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
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/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
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/// SignBitIsZero - Return true if the sign bit of Op is known to be zero. We
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/// use this predicate to simplify operations downstream.
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/// use this predicate to simplify operations downstream.
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bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
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bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
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// This predicate is not safe for vector operations.
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if (Op.getValueType().isVector())
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return false;
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unsigned BitWidth = Op.getValueSizeInBits();
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unsigned BitWidth = Op.getValueSizeInBits();
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return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
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return MaskedValueIsZero(Op, APInt::getSignBit(BitWidth), Depth);
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}
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}
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