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https://github.com/c64scene-ar/llvm-6502.git
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* Removed PreSelection pass because that is now done in the JIT
* Removed instruction scheduling as it is too slow to run in a JIT environment * Removed other passes because they aren't necessary and can slow JIT down git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6652 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -198,34 +198,24 @@ bool UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
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// generation for the UltraSparc.
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// generation for the UltraSparc.
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//
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//
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bool UltraSparc::addPassesToJITCompile(PassManager &PM) {
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bool UltraSparc::addPassesToJITCompile(PassManager &PM) {
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const TargetData &TD = getTargetData();
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PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
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TD.getPointerAlignment(), TD.getDoubleAlignment()));
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// Replace malloc and free instructions with library calls.
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// Do this after tracing until lli implements these lib calls.
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// For now, it will emulate malloc and free internally.
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PM.add(createLowerAllocationsPass());
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// FIXME: implement the switch instruction in the instruction selector.
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// FIXME: implement the switch instruction in the instruction selector.
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PM.add(createLowerSwitchPass());
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PM.add(createLowerSwitchPass());
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// Construct and initialize the MachineFunction object for this fn.
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// Construct and initialize the MachineFunction object for this fn.
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PM.add(createMachineCodeConstructionPass(*this));
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PM.add(createMachineCodeConstructionPass(*this));
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//Insert empty stackslots in the stack frame of each function
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//so %fp+offset-8 and %fp+offset-16 are empty slots now!
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PM.add(createStackSlotsPass(*this));
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// Specialize LLVM code for this target machine and then
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// run basic dataflow optimizations on LLVM code.
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#if 0
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if (!DisablePreSelect) {
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PM.add(createPreSelectionPass(*this));
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PM.add(createReassociatePass());
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PM.add(createLICMPass());
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PM.add(createGCSEPass());
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}
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#endif
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PM.add(createInstructionSelectionPass(*this));
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PM.add(createInstructionSelectionPass(*this));
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#if 0
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if (!DisableSched)
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PM.add(createInstructionSchedulingWithSSAPass(*this));
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#endif
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// new pass: convert Value* in MachineOperand to an unsigned register
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// new pass: convert Value* in MachineOperand to an unsigned register
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// this brings it in line with what the X86 JIT's RegisterAllocator expects
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// this brings it in line with what the X86 JIT's RegisterAllocator expects
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//PM.add(createAddRegNumToValuesPass());
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//PM.add(createAddRegNumToValuesPass());
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@ -233,10 +223,8 @@ bool UltraSparc::addPassesToJITCompile(PassManager &PM) {
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PM.add(getRegisterAllocator(*this));
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PM.add(getRegisterAllocator(*this));
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PM.add(getPrologEpilogInsertionPass());
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PM.add(getPrologEpilogInsertionPass());
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#if 0
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if (!DisablePeephole)
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if (!DisablePeephole)
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PM.add(createPeepholeOptsPass(*this));
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PM.add(createPeepholeOptsPass(*this));
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#endif
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return false; // success!
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return false; // success!
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}
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}
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