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Targets all now request ConstantFP to be legalized into TargetConstantFP.

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'fpimm' in .td files is now TargetConstantFP.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25771 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-29 06:26:08 +00:00
parent 08a90229ae
commit a54aa94197
5 changed files with 13 additions and 3 deletions
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2
lib/Target/IA64/IA64ISelDAGToDAG.cpp
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@ -419,7 +419,7 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
case ISD::SREM:
case ISD::UREM: return SelectDIV(Op);
case ISD::ConstantFP: {
case ISD::TargetConstantFP: {
SDOperand Chain = CurDAG->getEntryNode(); // this is a constant, so..
if (cast<ConstantFPSDNode>(N)->isExactlyValue(+0.0))

1
lib/Target/IA64/IA64ISelLowering.cpp
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@ -104,6 +104,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
computeRegisterProperties();
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
addLegalFPImmediate(+0.0);
addLegalFPImmediate(+1.0);
}

3
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -37,6 +37,9 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
// PowerPC has no intrinsics for these particular operations
setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
setOperationAction(ISD::MEMSET, MVT::Other, Expand);

3
lib/Target/TargetSelectionDAG.td
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@ -194,7 +194,8 @@ def node;
def srcvalue;
def imm : SDNode<"ISD::Constant" , SDTIntLeaf , [], "ConstantSDNode">;
def fpimm : SDNode<"ISD::ConstantFP", SDTFPLeaf , [], "ConstantFPSDNode">;
def fpimm : SDNode<"ISD::TargetConstantFP",
SDTFPLeaf, [], "ConstantFPSDNode">;
def vt : SDNode<"ISD::VALUETYPE" , SDTOther , [], "VTSDNode">;
def bb : SDNode<"ISD::BasicBlock", SDTOther , [], "BasicBlockSDNode">;
def cond : SDNode<"ISD::CONDCODE" , SDTOther , [], "CondCodeSDNode">;

7
lib/Target/X86/X86ISelLowering.cpp
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@ -45,7 +45,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setSchedulingPreference(SchedulingForRegPressure);
setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
setStackPointerRegisterToSaveRestore(X86::ESP);
// Set up the register classes.
addRegisterClass(MVT::i8, X86::R8RegisterClass);
addRegisterClass(MVT::i16, X86::R16RegisterClass);
@ -213,6 +213,10 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::FNEG , MVT::f32, Expand);
setOperationAction(ISD::FREM , MVT::f32, Expand);
// Expand FP immediates into loads from the stack, except for the special
// cases we handle.
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
addLegalFPImmediate(+0.0); // xorps / xorpd
} else {
// Set up the FP register classes.
@ -228,6 +232,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
setOperationAction(ISD::FCOS , MVT::f64 , Expand);
}
setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
addLegalFPImmediate(+0.0); // FLD0
addLegalFPImmediate(+1.0); // FLD1
addLegalFPImmediate(-0.0); // FLD0/FCHS