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https://github.com/c64scene-ar/llvm-6502.git
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NEON VLD4(all lanes) assembly parsing and encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148884 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
6cd6a6824f
commit
a57a36abe7
@ -191,6 +191,25 @@ def VecListThreeQAllLanes : RegisterOperand<DPR,
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"printVectorListThreeSpacedAllLanes"> {
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let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
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}
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// Register list of four D registers, with "all lanes" subscripting.
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def VecListFourDAllLanesAsmOperand : AsmOperandClass {
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let Name = "VecListFourDAllLanes";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
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let ParserMatchClass = VecListFourDAllLanesAsmOperand;
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}
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// Register list of four D registers spaced by 2 (four sequential Q regs).
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def VecListFourQAllLanesAsmOperand : AsmOperandClass {
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let Name = "VecListFourQAllLanes";
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let ParserMethod = "parseVectorList";
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let RenderMethod = "addVecListOperands";
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}
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def VecListFourQAllLanes : RegisterOperand<DPR,
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"printVectorListFourSpacedAllLanes"> {
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let ParserMatchClass = VecListFourQAllLanesAsmOperand;
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}
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// Register list of one D register, with byte lane subscripting.
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@ -6333,6 +6352,65 @@ def VST3qWB_register_Asm_32 :
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(ins VecListThreeQ:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD4 all-lanes pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqWB_fixed_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqWB_fixed_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPqWB_fixed_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr, pred:$p)>;
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def VLD4DUPdWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4DUPdWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4DUPdWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourDAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4DUPqWB_register_Asm_8 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4DUPqWB_register_Asm_16 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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def VLD4DUPqWB_register_Asm_32 :
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NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
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(ins VecListFourQAllLanes:$list, addrmode6:$addr,
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rGPR:$Rm, pred:$p)>;
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// VLD4 single-lane pseudo-instructions. These need special handling for
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// the lane index that an InstAlias can't handle, so we use these instead.
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def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
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@ -1142,6 +1142,16 @@ public:
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return VectorList.Count == 3;
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}
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bool isVecListFourDAllLanes() const {
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if (!isSingleSpacedVectorAllLanes()) return false;
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return VectorList.Count == 4;
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}
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bool isVecListFourQAllLanes() const {
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if (!isDoubleSpacedVectorAllLanes()) return false;
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return VectorList.Count == 4;
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}
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bool isSingleSpacedVectorIndexed() const {
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return Kind == k_VectorListIndexed && !VectorList.isDoubleSpaced;
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}
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@ -5427,6 +5437,26 @@ static unsigned getRealVLDOpcode(unsigned Opc, unsigned &Spacing) {
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case ARM::VLD4LNqAsm_16: Spacing = 2; return ARM::VLD4LNq16;
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case ARM::VLD4LNqAsm_32: Spacing = 2; return ARM::VLD4LNq32;
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// VLD4DUP
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case ARM::VLD4DUPdWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
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case ARM::VLD4DUPdWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
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case ARM::VLD4DUPdWB_fixed_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
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case ARM::VLD4DUPqWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4DUPq8_UPD;
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case ARM::VLD4DUPqWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4DUPq16_UPD;
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case ARM::VLD4DUPqWB_fixed_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
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case ARM::VLD4DUPdWB_register_Asm_8: Spacing = 1; return ARM::VLD4DUPd8_UPD;
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case ARM::VLD4DUPdWB_register_Asm_16: Spacing = 1; return ARM::VLD4DUPd16_UPD;
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case ARM::VLD4DUPdWB_register_Asm_32: Spacing = 1; return ARM::VLD4DUPd32_UPD;
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case ARM::VLD4DUPqWB_register_Asm_8: Spacing = 2; return ARM::VLD4DUPq8_UPD;
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case ARM::VLD4DUPqWB_register_Asm_16: Spacing = 2; return ARM::VLD4DUPq16_UPD;
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case ARM::VLD4DUPqWB_register_Asm_32: Spacing = 2; return ARM::VLD4DUPq32_UPD;
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case ARM::VLD4DUPdAsm_8: Spacing = 1; return ARM::VLD4DUPd8;
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case ARM::VLD4DUPdAsm_16: Spacing = 1; return ARM::VLD4DUPd16;
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case ARM::VLD4DUPdAsm_32: Spacing = 1; return ARM::VLD4DUPd32;
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case ARM::VLD4DUPqAsm_8: Spacing = 2; return ARM::VLD4DUPq8;
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case ARM::VLD4DUPqAsm_16: Spacing = 2; return ARM::VLD4DUPq16;
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case ARM::VLD4DUPqAsm_32: Spacing = 2; return ARM::VLD4DUPq32;
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// VLD4
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case ARM::VLD4dWB_fixed_Asm_8: Spacing = 1; return ARM::VLD4d8_UPD;
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case ARM::VLD4dWB_fixed_Asm_16: Spacing = 1; return ARM::VLD4d16_UPD;
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@ -6233,7 +6263,84 @@ processInstruction(MCInst &Inst,
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return true;
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}
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// VLD4 multiple 3-element structure instructions.
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// VLD4DUP single 3-element structure to all lanes instructions.
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case ARM::VLD4DUPdAsm_8:
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case ARM::VLD4DUPdAsm_16:
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case ARM::VLD4DUPdAsm_32:
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case ARM::VLD4DUPqAsm_8:
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case ARM::VLD4DUPqAsm_16:
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case ARM::VLD4DUPqAsm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD4DUPdWB_fixed_Asm_8:
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case ARM::VLD4DUPdWB_fixed_Asm_16:
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case ARM::VLD4DUPdWB_fixed_Asm_32:
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case ARM::VLD4DUPqWB_fixed_Asm_8:
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case ARM::VLD4DUPqWB_fixed_Asm_16:
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case ARM::VLD4DUPqWB_fixed_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
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TmpInst.addOperand(Inst.getOperand(3)); // CondCode
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TmpInst.addOperand(Inst.getOperand(4));
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Inst = TmpInst;
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return true;
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}
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case ARM::VLD4DUPdWB_register_Asm_8:
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case ARM::VLD4DUPdWB_register_Asm_16:
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case ARM::VLD4DUPdWB_register_Asm_32:
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case ARM::VLD4DUPqWB_register_Asm_8:
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case ARM::VLD4DUPqWB_register_Asm_16:
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case ARM::VLD4DUPqWB_register_Asm_32: {
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MCInst TmpInst;
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unsigned Spacing;
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TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
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TmpInst.addOperand(Inst.getOperand(0)); // Vd
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 2));
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TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
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Spacing * 3));
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TmpInst.addOperand(Inst.getOperand(1)); // Rn
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TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
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TmpInst.addOperand(Inst.getOperand(2)); // alignment
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TmpInst.addOperand(Inst.getOperand(3)); // Rm
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TmpInst.addOperand(Inst.getOperand(4)); // CondCode
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TmpInst.addOperand(Inst.getOperand(5));
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Inst = TmpInst;
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return true;
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}
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// VLD4 multiple 4-element structure instructions.
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case ARM::VLD4dAsm_8:
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case ARM::VLD4dAsm_16:
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case ARM::VLD4dAsm_32:
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@ -1078,6 +1078,18 @@ void ARMInstPrinter::printVectorListThreeAllLanes(const MCInst *MI,
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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}
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void ARMInstPrinter::printVectorListFourAllLanes(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 1) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 3) << "[]}";
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}
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void ARMInstPrinter::printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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@ -1105,7 +1117,19 @@ void ARMInstPrinter::printVectorListThreeSpacedAllLanes(const MCInst *MI,
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[]}";
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[]}";
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}
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void ARMInstPrinter::printVectorListFourSpacedAllLanes(const MCInst *MI,
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unsigned OpNum,
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raw_ostream &O) {
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// Normally, it's not safe to use register enum values directly with
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// addition to get the next register, but for VFP registers, the
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// sort order is guaranteed because they're all of the form D<n>.
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O << "{" << getRegisterName(MI->getOperand(OpNum).getReg()) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 2) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 4) << "[], "
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<< getRegisterName(MI->getOperand(OpNum).getReg() + 6) << "[]}";
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}
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void ARMInstPrinter::printVectorListThreeSpaced(const MCInst *MI,
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@ -141,12 +141,16 @@ public:
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raw_ostream &O);
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void printVectorListThreeAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListFourAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListTwoSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListTwoSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListFourSpacedAllLanes(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListThreeSpaced(const MCInst *MI, unsigned OpNum,
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raw_ostream &O);
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void printVectorListFourSpaced(const MCInst *MI, unsigned OpNum,
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@ -412,6 +412,46 @@
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@ CHECK: vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4 @ encoding: [0xc4,0x1b,0xe9,0xf4]
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vld4.8 {d16[], d17[], d18[], d19[]}, [r1]
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vld4.16 {d16[], d17[], d18[], d19[]}, [r2]
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vld4.32 {d16[], d17[], d18[], d19[]}, [r3]
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vld4.8 {d17[], d19[], d21[], d23[]}, [r7]
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vld4.16 {d17[], d19[], d21[], d23[]}, [r7]
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vld4.32 {d16[], d18[], d20[], d22[]}, [r8]
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vld4.s8 {d16[], d17[], d18[], d19[]}, [r1]!
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vld4.s16 {d16[], d17[], d18[], d19[]}, [r2]!
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vld4.s32 {d16[], d17[], d18[], d19[]}, [r3]!
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vld4.u8 {d17[], d19[], d21[], d23[]}, [r7]!
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vld4.u16 {d17[], d19[], d21[], d23[]}, [r7]!
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vld4.u32 {d16[], d18[], d20[], d22[]}, [r8]!
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vld4.p8 {d16[], d17[], d18[], d19[]}, [r1], r8
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vld4.p16 {d16[], d17[], d18[], d19[]}, [r2], r7
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vld4.f32 {d16[], d17[], d18[], d19[]}, [r3], r5
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vld4.i8 {d16[], d18[], d20[], d22[]}, [r6], r3
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vld4.i16 {d16[], d18[], d20[], d22[]}, [r6], r3
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vld4.i32 {d17[], d19[], d21[], d23[]}, [r9], r4
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@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1] @ encoding: [0x0f,0x0f,0xe1,0xf4]
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@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2] @ encoding: [0x4f,0x0f,0xe2,0xf4]
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||||
@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3] @ encoding: [0x8f,0x0f,0xe3,0xf4]
|
||||
@ CHECK: vld4.8 {d17[], d19[], d21[], d23[]}, [r7] @ encoding: [0x2f,0x1f,0xe7,0xf4]
|
||||
@ CHECK: vld4.16 {d17[], d19[], d21[], d23[]}, [r7] @ encoding: [0x6f,0x1f,0xe7,0xf4]
|
||||
@ CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r8] @ encoding: [0xaf,0x0f,0xe8,0xf4]
|
||||
@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1]! @ encoding: [0x0d,0x0f,0xe1,0xf4]
|
||||
@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2]! @ encoding: [0x4d,0x0f,0xe2,0xf4]
|
||||
@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3]! @ encoding: [0x8d,0x0f,0xe3,0xf4]
|
||||
@ CHECK: vld4.8 {d17[], d18[], d19[], d20[]}, [r7]! @ encoding: [0x2d,0x1f,0xe7,0xf4]
|
||||
@ CHECK: vld4.16 {d17[], d18[], d19[], d20[]}, [r7]! @ encoding: [0x6d,0x1f,0xe7,0xf4]
|
||||
@ CHECK: vld4.32 {d16[], d18[], d20[], d22[]}, [r8]! @ encoding: [0xad,0x0f,0xe8,0xf4]
|
||||
@ CHECK: vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8 @ encoding: [0x08,0x0f,0xe1,0xf4]
|
||||
@ CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7 @ encoding: [0x47,0x0f,0xe2,0xf4]
|
||||
@ CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5 @ encoding: [0x85,0x0f,0xe3,0xf4]
|
||||
@ CHECK: vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3 @ encoding: [0x23,0x0f,0xe6,0xf4]
|
||||
@ CHECK: vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3 @ encoding: [0x63,0x0f,0xe6,0xf4]
|
||||
@ CHECK: vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4 @ encoding: [0xa4,0x1f,0xe9,0xf4]
|
||||
|
||||
@ Handle 'Q' registers in register lists as if the sub-reg D regs were
|
||||
@ specified instead.
|
||||
vld1.8 {q3}, [r9]
|
||||
|
||||
Loading…
Reference in New Issue
Block a user