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initial hack at a dag->dag instruction selector. This is obviously woefully
incomplete, but it is a start. It handles basic argument/retval stuff, immediates, add and sub. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22836 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d1c4626e14
commit
a5a91b1026
325
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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325
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
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//===-- PPC32ISelDAGToDAG.cpp - PPC32 pattern matching inst selector ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a pattern matching instruction selector for 32 bit PowerPC,
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// converting from a legalized dag to a PPC dag.
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//
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//===----------------------------------------------------------------------===//
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#include "PowerPC.h"
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#include "PPC32TargetMachine.h"
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#include "PPC32ISelLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetOptions.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/MathExtras.h"
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using namespace llvm;
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namespace {
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Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
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Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
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Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
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//===--------------------------------------------------------------------===//
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/// PPC32DAGToDAGISel - PPC32 specific code to select PPC32 machine
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/// instructions for SelectionDAG operations.
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///
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class PPC32DAGToDAGISel : public SelectionDAGISel {
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PPC32TargetLowering PPC32Lowering;
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unsigned GlobalBaseReg;
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bool GlobalBaseInitialized;
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public:
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PPC32DAGToDAGISel(TargetMachine &TM)
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: SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM) {}
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/// runOnFunction - Override this function in order to reset our
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/// per-function variables.
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseInitialized = false;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand Select(SDOperand Op);
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SDNode *SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic = false,
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bool Negate = false);
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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// Codegen the basic block.
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Select(DAG.getRoot());
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DAG.RemoveDeadNodes();
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DAG.viewGraph();
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}
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virtual const char *getPassName() const {
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return "PowerPC DAG->DAG Pattern Instruction Selection";
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}
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};
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}
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// Immediate constant composers.
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// Lo16 - grabs the lo 16 bits from a 32 bit constant.
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// Hi16 - grabs the hi 16 bits from a 32 bit constant.
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// HA16 - computes the hi bits required if the lo bits are add/subtracted in
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// arithmethically.
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static unsigned Lo16(unsigned x) { return x & 0x0000FFFF; }
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static unsigned Hi16(unsigned x) { return Lo16(x >> 16); }
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static unsigned HA16(unsigned x) { return Hi16((signed)x - (signed short)x); }
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// isIntImmediate - This method tests to see if a constant operand.
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// If so Imm will receive the 32 bit value.
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static bool isIntImmediate(SDOperand N, unsigned& Imm) {
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
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Imm = (unsigned)CN->getSignExtended();
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return true;
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}
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return false;
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}
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// SelectIntImmediateExpr - Choose code for integer operations with an immediate
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// operand.
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SDNode *PPC32DAGToDAGISel::SelectIntImmediateExpr(SDOperand LHS, SDOperand RHS,
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unsigned OCHi, unsigned OCLo,
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bool IsArithmetic,
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bool Negate) {
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// Check to make sure this is a constant.
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(RHS);
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// Exit if not a constant.
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if (!CN) return 0;
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// Extract immediate.
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unsigned C = (unsigned)CN->getValue();
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// Negate if required (ISD::SUB).
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if (Negate) C = -C;
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// Get the hi and lo portions of constant.
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unsigned Hi = IsArithmetic ? HA16(C) : Hi16(C);
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unsigned Lo = Lo16(C);
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// If two instructions are needed and usage indicates it would be better to
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// load immediate into a register, bail out.
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if (Hi && Lo && CN->use_size() > 2) return false;
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// Select the first operand.
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SDOperand Opr0 = Select(LHS);
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if (Lo) // Add in the lo-part.
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Opr0 = CurDAG->getTargetNode(OCLo, MVT::i32, Opr0, getI32Imm(Lo));
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if (Hi) // Add in the hi-part.
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Opr0 = CurDAG->getTargetNode(OCHi, MVT::i32, Opr0, getI32Imm(Hi));
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return Opr0.Val;
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}
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// Select - Convert the specified operand from a target-independent to a
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// target-specific node if it hasn't already been changed.
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SDOperand PPC32DAGToDAGISel::Select(SDOperand Op) {
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SDNode *N = Op.Val;
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if (N->getOpcode() >= ISD::BUILTIN_OP_END)
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return Op; // Already selected.
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switch (N->getOpcode()) {
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default:
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std::cerr << "Cannot yet select: ";
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N->dump();
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std::cerr << "\n";
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abort();
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case ISD::EntryToken: // These leaves remain the same.
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case ISD::UNDEF:
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return Op;
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case ISD::TokenFactor: {
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SDOperand New;
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if (N->getNumOperands() == 2) {
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SDOperand Op0 = Select(N->getOperand(0));
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SDOperand Op1 = Select(N->getOperand(1));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Op0, Op1);
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} else {
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std::vector<SDOperand> Ops;
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for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
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Ops.push_back(Select(N->getOperand(0)));
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New = CurDAG->getNode(ISD::TokenFactor, MVT::Other, Ops);
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}
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if (New.Val != N) {
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CurDAG->ReplaceAllUsesWith(N, New.Val);
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N = New.Val;
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}
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break;
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}
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case ISD::CopyFromReg: {
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SDOperand Chain = Select(N->getOperand(0));
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if (Chain == N->getOperand(0)) return Op; // No change
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SDOperand New = CurDAG->getCopyFromReg(Chain,
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cast<RegisterSDNode>(N->getOperand(1))->getReg(), N->getValueType(0));
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return New.getValue(Op.ResNo);
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}
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case ISD::CopyToReg: {
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SDOperand Chain = Select(N->getOperand(0));
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SDOperand Reg = N->getOperand(1);
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SDOperand Val = Select(N->getOperand(2));
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if (Chain != N->getOperand(0) || Val != N->getOperand(2)) {
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SDOperand New = CurDAG->getNode(ISD::CopyToReg, MVT::Other,
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Chain, Reg, Val);
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CurDAG->ReplaceAllUsesWith(N, New.Val);
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N = New.Val;
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}
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break;
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}
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case ISD::Constant: {
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assert(N->getValueType(0) == MVT::i32);
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unsigned v = (unsigned)cast<ConstantSDNode>(N)->getValue();
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if ((unsigned)(short)v == v) {
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::LI, getI32Imm(v));
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break;
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} else {
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SDOperand Top = CurDAG->getTargetNode(PPC::LIS, MVT::i32,
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getI32Imm(unsigned(v) >> 16));
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CurDAG->SelectNodeTo(N, MVT::i32, PPC::ORI, Top, getI32Imm(v & 0xFFFF));
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break;
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}
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}
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case ISD::ADD: {
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true)) {
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CurDAG->ReplaceAllUsesWith(N, I);
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, Ty, PPC::ADD, Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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}
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break;
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::MUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMADD : PPC::FMADDS,
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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}
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}
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FADD : PPC::FADDS,
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Select(N->getOperand(0)), Select(N->getOperand(1)));
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break;
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}
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case ISD::SUB: {
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MVT::ValueType Ty = N->getValueType(0);
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if (Ty == MVT::i32) {
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unsigned Imm;
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if (isIntImmediate(N->getOperand(0), Imm) && isInt16(Imm)) {
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CurDAG->SelectNodeTo(N, Ty, PPC::SUBFIC, Select(N->getOperand(1)),
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getI32Imm(Lo16(Imm)));
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break;
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}
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if (SDNode *I = SelectIntImmediateExpr(N->getOperand(0), N->getOperand(1),
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PPC::ADDIS, PPC::ADDI, true, true)) {
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CurDAG->ReplaceAllUsesWith(N, I);
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N = I;
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} else {
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CurDAG->SelectNodeTo(N, Ty, PPC::SUBF, Select(N->getOperand(1)),
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Select(N->getOperand(0)));
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}
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break;
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}
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if (!NoExcessFPPrecision) { // Match FMA ops
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if (N->getOperand(0).getOpcode() == ISD::MUL &&
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N->getOperand(0).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS,
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Select(N->getOperand(0).getOperand(0)),
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Select(N->getOperand(0).getOperand(1)),
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Select(N->getOperand(1)));
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break;
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} else if (N->getOperand(1).getOpcode() == ISD::MUL &&
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N->getOperand(1).Val->hasOneUse()) {
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++FusedFP; // Statistic
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS,
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Select(N->getOperand(1).getOperand(0)),
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Select(N->getOperand(1).getOperand(1)),
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Select(N->getOperand(0)));
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break;
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}
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}
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CurDAG->SelectNodeTo(N, Ty, Ty == MVT::f64 ? PPC::FSUB : PPC::FSUBS,
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Select(N->getOperand(0)),
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Select(N->getOperand(1)));
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break;
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}
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case ISD::RET: {
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SDOperand Chain = Select(N->getOperand(0)); // Token chain.
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if (N->getNumOperands() > 1) {
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SDOperand Val = Select(N->getOperand(1));
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switch (N->getOperand(1).getValueType()) {
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default: assert(0 && "Unknown return type!");
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case MVT::f64:
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case MVT::f32:
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Chain = CurDAG->getCopyToReg(Chain, PPC::F1, Val);
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break;
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case MVT::i32:
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Chain = CurDAG->getCopyToReg(Chain, PPC::R3, Val);
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break;
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}
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if (N->getNumOperands() > 2) {
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assert(N->getOperand(1).getValueType() == MVT::i32 &&
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N->getOperand(2).getValueType() == MVT::i32 &&
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N->getNumOperands() == 2 && "Unknown two-register ret value!");
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Val = Select(N->getOperand(2));
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Chain = CurDAG->getCopyToReg(Chain, PPC::R4, Val);
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}
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}
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// Finally, select this to a blr (return) instruction.
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CurDAG->SelectNodeTo(N, MVT::Other, PPC::BLR, Chain);
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break;
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}
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}
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return SDOperand(N, 0);
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}
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/// createPPC32ISelDag - This pass converts a legalized DAG into a
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/// PowerPC-specific DAG, ready for instruction scheduling.
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///
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FunctionPass *llvm::createPPC32ISelDag(TargetMachine &TM) {
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return new PPC32DAGToDAGISel(TM);
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}
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