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R600/SI: Add basic DAG combines for fp_class
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225306 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
parent
b6520ab625
commit
a5b2b64292
@ -218,7 +218,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setTargetDAGCombine(ISD::FMAXNUM);
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setTargetDAGCombine(ISD::SELECT_CC);
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setTargetDAGCombine(ISD::SETCC);
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setTargetDAGCombine(ISD::OR);
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setTargetDAGCombine(ISD::UINT_TO_FP);
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// All memory operations. Some folding on the pointer operand is done to help
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@ -1302,6 +1302,49 @@ SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
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return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
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}
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SDValue SITargetLowering::performOrCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDValue LHS = N->getOperand(0);
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SDValue RHS = N->getOperand(1);
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// or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
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if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
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RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
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SDValue Src = LHS.getOperand(0);
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if (Src != RHS.getOperand(0))
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return SDValue();
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const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
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const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
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if (!CLHS || !CRHS)
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return SDValue();
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// Only 10 bits are used.
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static const uint32_t MaxMask = 0x3ff;
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uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
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return DAG.getNode(AMDGPUISD::FP_CLASS, SDLoc(N), MVT::i1,
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Src, DAG.getConstant(NewMask, MVT::i32));
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}
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return SDValue();
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}
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SDValue SITargetLowering::performClassCombine(SDNode *N,
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DAGCombinerInfo &DCI) const {
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SelectionDAG &DAG = DCI.DAG;
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SDValue Mask = N->getOperand(1);
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// fp_class x, 0 -> false
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if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
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if (CMask->isNullValue())
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return DAG.getConstant(0, MVT::i1);
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}
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return SDValue();
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}
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static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
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switch (Opc) {
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case ISD::FMAXNUM:
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@ -1531,6 +1574,10 @@ SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
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}
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break;
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}
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case ISD::OR:
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return performOrCombine(N, DCI);
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case AMDGPUISD::FP_CLASS:
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return performClassCombine(N, DCI);
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}
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return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
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}
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@ -58,6 +58,8 @@ class SITargetLowering : public AMDGPUTargetLowering {
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SDValue performSHLPtrCombine(SDNode *N,
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unsigned AS,
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DAGCombinerInfo &DCI) const;
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SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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SDValue performMin3Max3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
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@ -331,5 +331,167 @@ define void @test_class_lit_constant_dynamic_mask_f64(i32 addrspace(1)* %out, i3
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ret void
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}
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; SI-LABEL: {{^}}test_fold_or_class_f32_0:
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; SI-NOT: v_cmp_class
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; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 3{{$}}
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 3) #1
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%or = or i1 %class0, %class1
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%sext = sext i1 %or to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_fold_or3_class_f32_0:
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; SI-NOT: v_cmp_class
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; SI: v_cmp_class_f32_e64 s{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_fold_or3_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
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%class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
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%or.0 = or i1 %class0, %class1
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%or.1 = or i1 %or.0, %class2
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%sext = sext i1 %or.1 to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_fold_or_all_tests_class_f32_0:
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; SI-NOT: v_cmp_class
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; SI: v_mov_b32_e32 [[MASK:v[0-9]+]], 0x3ff{{$}}
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; SI: v_cmp_class_f32_e32 vcc, v{{[0-9]+}}, [[MASK]]{{$}}
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_fold_or_all_tests_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 1) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 2) #1
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%class2 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
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%class3 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1
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%class4 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 16) #1
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%class5 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 32) #1
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%class6 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 64) #1
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%class7 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 128) #1
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%class8 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 256) #1
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%class9 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 512) #1
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%or.0 = or i1 %class0, %class1
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%or.1 = or i1 %or.0, %class2
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%or.2 = or i1 %or.1, %class3
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%or.3 = or i1 %or.2, %class4
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%or.4 = or i1 %or.3, %class5
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%or.5 = or i1 %or.4, %class6
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%or.6 = or i1 %or.5, %class7
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%or.7 = or i1 %or.6, %class8
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%or.8 = or i1 %or.7, %class9
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%sext = sext i1 %or.8 to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_fold_or_class_f32_1:
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; SI-NOT: v_cmp_class
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; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 12{{$}}
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_fold_or_class_f32_1(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 8) #1
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%or = or i1 %class0, %class1
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%sext = sext i1 %or to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_fold_or_class_f32_2:
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; SI-NOT: v_cmp_class
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; SI: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 7{{$}}
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; SI-NOT: v_cmp_class
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; SI: s_endpgm
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define void @test_fold_or_class_f32_2(i32 addrspace(1)* %out, float addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 7) #1
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%or = or i1 %class0, %class1
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%sext = sext i1 %or to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_no_fold_or_class_f32_0:
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; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, 4{{$}}
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; SI-DAG: v_cmp_class_f32_e64 {{s\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}}, 8{{$}}
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; SI: s_or_b64
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; SI: s_endpgm
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define void @test_no_fold_or_class_f32_0(i32 addrspace(1)* %out, float addrspace(1)* %in, float %b) #0 {
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%tid = call i32 @llvm.r600.read.tidig.x() #1
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%gep.in = getelementptr float addrspace(1)* %in, i32 %tid
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%gep.out = getelementptr i32 addrspace(1)* %out, i32 %tid
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%a = load float addrspace(1)* %gep.in
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%class0 = call i1 @llvm.AMDGPU.class.f32(float %a, i32 4) #1
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%class1 = call i1 @llvm.AMDGPU.class.f32(float %b, i32 8) #1
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%or = or i1 %class0, %class1
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%sext = sext i1 %or to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_class_0_f32:
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; SI-NOT: v_cmp_class
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; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
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; SI-NEXT: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @test_class_0_f32(i32 addrspace(1)* %out, float %a) #0 {
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%result = call i1 @llvm.AMDGPU.class.f32(float %a, i32 0) #1
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%sext = sext i1 %result to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}test_class_0_f64:
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; SI-NOT: v_cmp_class
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; SI: v_mov_b32_e32 [[RESULT:v[0-9]+]], 0{{$}}
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; SI: buffer_store_dword [[RESULT]]
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; SI: s_endpgm
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define void @test_class_0_f64(i32 addrspace(1)* %out, double %a) #0 {
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%result = call i1 @llvm.AMDGPU.class.f64(double %a, i32 0) #1
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%sext = sext i1 %result to i32
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store i32 %sext, i32 addrspace(1)* %out, align 4
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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