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- Revert some changes from 85044, 85045, and 85047 that broke x86_64 tests and

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bootstrapping. It's not safe to leave identity subreg_to_reg and insert_subreg
  around.
- Relax register scavenging to allow use of partially "not-live" registers. It's
  common for targets to operate on registers where the top bits are undef. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
     = d0
  When the insert_subreg is eliminated by the coalescer, the scavenger used to
  complain. The previous fix was to keep to insert_subreg around. But that's
  brittle and it's overly conservative when we want to use the scavenger to 
  allocate registers. It's actually legal and desirable for other instructions
  to use the "undef" part of d0. e.g.
  s0 =
  d0 = insert_subreg d0<undef>, s0, 1
  ...
  s1 =
     = s1
     = d0
  We probably need add a "partial-undef" marker on machine operand so the
  machine verifier would not complain.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85091 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2009-10-26 04:56:07 +00:00
parent 85def16079
commit a5dc45e3c8
5 changed files with 218 additions and 45 deletions
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28
include/llvm/Target/TargetInstrInfo.h
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@@ -145,30 +145,20 @@ public:
/// isIdentityCopy - Return true if the instruction is a copy (or
/// extract_subreg, insert_subreg, subreg_to_reg) where the source and
/// destination registers are the same.
bool isIdentityCopy(const MachineInstr &MI,
unsigned &SrcReg, unsigned &DstReg,
unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
bool isIdentityCopy(const MachineInstr &MI) const {
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
SrcReg == DstReg)
return true;
if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG) {
DstReg = MI.getOperand(0).getReg();
DstSubIdx = MI.getOperand(0).getSubReg();
SrcReg = MI.getOperand(1).getReg();
SrcSubIdx = MI.getOperand(1).getSubReg();
return DstReg == SrcReg;
}
if (MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) {
DstReg = MI.getOperand(0).getReg();
DstSubIdx = MI.getOperand(0).getSubReg();
SrcReg = MI.getOperand(2).getReg();
SrcSubIdx = MI.getOperand(2).getSubReg();
return DstReg == SrcReg;
}
if (MI.getOpcode() == TargetInstrInfo::EXTRACT_SUBREG &&
MI.getOperand(0).getReg() == MI.getOperand(1).getReg())
return true;
if ((MI.getOpcode() == TargetInstrInfo::INSERT_SUBREG ||
MI.getOpcode() == TargetInstrInfo::SUBREG_TO_REG) &&
MI.getOperand(0).getReg() == MI.getOperand(2).getReg())
return true;
return false;
}