6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-01 00:17:01 +00:00
Code Issues Projects Releases Wiki Activity

Start TargetRegisterClass indices at 0 instead of 1, so that

Browse Source 
MachineRegisterInfo doesn't have to confusingly allocate an extra
entry.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106296 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dan Gohman
2010-06-18 18:13:55 +00:00
parent df50d7e238
commit a606d955de
9 changed files with 56 additions and 49 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@@ -35,7 +35,7 @@ class MachineRegisterInfo {
/// RegClassVRegMap - This vector acts as a map from TargetRegisterClass to
/// virtual registers. For each target register class, it keeps a list of
/// virtual registers belonging to the class.
std::vector<std::vector<unsigned> > RegClass2VRegMap;
std::vector<unsigned> *RegClass2VRegMap;
/// RegAllocHints - This vector records register allocation hints for virtual
/// registers. For each virtual register, it keeps a register and hint type