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Add LOAD NEGATIVE instruction
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76032 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -82,7 +82,6 @@ def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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let isTwoAddress = 1 in {
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let Defs = [PSW] in {
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// FIXME: Add peephole for fneg(fabs) => load negative
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def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"lpebr\t{$dst}",
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@ -93,6 +92,15 @@ def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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[(set FP64:$dst, (fabs FP64:$src)),
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(implicit PSW)]>;
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def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
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"lnebr\t{$dst}",
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[(set FP32:$dst, (fneg(fabs FP32:$src))),
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(implicit PSW)]>;
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def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
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"lndbr\t{$dst}",
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[(set FP64:$dst, (fneg(fabs FP64:$src))),
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(implicit PSW)]>;
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let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
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def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
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"aebr\t{$dst, $src2}",
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