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Teach the DAGCombiner how to fold concat_vector nodes when the input is two
BUILD_VECTOR nodes, e.g.: (concat_vectors (BUILD_VECTOR a1, a2, a3, a4), (BUILD_VECTOR b1, b2, b3, b4)) -> (BUILD_VECTOR a1, a2, a3, a4, b1, b2, b3, b4) This fixes an issue with AVX, where a sequence was not recognized as a 256-bit vbroadcast due to the concat_vectors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201158 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Robert Lougher
parent
79ced8c5fa
commit
a63585a8f5
@ -10136,6 +10136,26 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
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}
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}
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// fold (concat_vectors (BUILD_VECTOR A, B, ...), (BUILD_VECTOR C, D, ...))
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// -> (BUILD_VECTOR A, B, ..., C, D, ...)
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if (N->getNumOperands() == 2 &&
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N->getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
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N->getOperand(1).getOpcode() == ISD::BUILD_VECTOR) {
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EVT VT = N->getValueType(0);
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SDValue N0 = N->getOperand(0);
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SDValue N1 = N->getOperand(1);
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SmallVector<SDValue, 8> Opnds;
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unsigned BuildVecNumElts = N0.getNumOperands();
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N0.getOperand(i));
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for (unsigned i = 0; i != BuildVecNumElts; ++i)
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Opnds.push_back(N1.getOperand(i));
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return DAG.getNode(ISD::BUILD_VECTOR, SDLoc(N), VT, &Opnds[0],
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Opnds.size());
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}
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// Type legalization of vectors and DAG canonicalization of SHUFFLE_VECTOR
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// nodes often generate nop CONCAT_VECTOR nodes.
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// Scan the CONCAT_VECTOR operands and look for a CONCAT operations that
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@ -141,3 +141,66 @@ entry:
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ret <4 x float> %t
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}
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; These tests check that a vbroadcast instruction is used when we have a splat
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; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
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; (via the insertelements).
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; CHECK-LABEL: splat_concat1
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastss (%
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; CHECK-NEXT: ret
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define <8 x float> @splat_concat1(float* %p) {
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%1 = load float* %p, align 4
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%3 = insertelement <4 x float> %2, float %1, i32 1
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%4 = insertelement <4 x float> %3, float %1, i32 2
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%5 = insertelement <4 x float> %4, float %1, i32 3
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%6 = shufflevector <4 x float> %5, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %6
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}
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; CHECK-LABEL: splat_concat2
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastss (%
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; CHECK-NEXT: ret
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define <8 x float> @splat_concat2(float* %p) {
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%1 = load float* %p, align 4
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%2 = insertelement <4 x float> undef, float %1, i32 0
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%3 = insertelement <4 x float> %2, float %1, i32 1
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%4 = insertelement <4 x float> %3, float %1, i32 2
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%5 = insertelement <4 x float> %4, float %1, i32 3
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%6 = insertelement <4 x float> undef, float %1, i32 0
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%7 = insertelement <4 x float> %6, float %1, i32 1
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%8 = insertelement <4 x float> %7, float %1, i32 2
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%9 = insertelement <4 x float> %8, float %1, i32 3
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%10 = shufflevector <4 x float> %5, <4 x float> %9, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x float> %10
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}
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; CHECK-LABEL: splat_concat3
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastsd (%
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; CHECK-NEXT: ret
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define <4 x double> @splat_concat3(double* %p) {
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%1 = load double* %p, align 8
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%2 = insertelement <2 x double> undef, double %1, i32 0
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%3 = insertelement <2 x double> %2, double %1, i32 1
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%4 = shufflevector <2 x double> %3, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x double> %4
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}
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; CHECK-LABEL: splat_concat4
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastsd (%
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; CHECK-NEXT: ret
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define <4 x double> @splat_concat4(double* %p) {
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%1 = load double* %p, align 8
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%2 = insertelement <2 x double> undef, double %1, i32 0
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%3 = insertelement <2 x double> %2, double %1, i32 1
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%4 = insertelement <2 x double> undef, double %1, i32 0
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%5 = insertelement <2 x double> %2, double %1, i32 1
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%6 = shufflevector <2 x double> %3, <2 x double> %5, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x double> %6
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}
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@ -355,3 +355,61 @@ define <16 x i8> @_inreg16xi8(<16 x i8> %a) {
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%b = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> zeroinitializer
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ret <16 x i8> %b
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}
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; These tests check that a vbroadcast instruction is used when we have a splat
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; formed from a concat_vectors (via the shufflevector) of two BUILD_VECTORs
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; (via the insertelements).
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; CHECK-LABEL: splat_concat1
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastss
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; CHECK-NEXT: ret
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define <8 x float> @splat_concat1(float %f) {
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%1 = insertelement <4 x float> undef, float %f, i32 0
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%2 = insertelement <4 x float> %1, float %f, i32 1
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%3 = insertelement <4 x float> %2, float %f, i32 2
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%4 = insertelement <4 x float> %3, float %f, i32 3
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%5 = shufflevector <4 x float> %4, <4 x float> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 0, i32 1, i32 2, i32 3>
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ret <8 x float> %5
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}
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; CHECK-LABEL: splat_concat2
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastss
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; CHECK-NEXT: ret
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define <8 x float> @splat_concat2(float %f) {
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%1 = insertelement <4 x float> undef, float %f, i32 0
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%2 = insertelement <4 x float> %1, float %f, i32 1
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%3 = insertelement <4 x float> %2, float %f, i32 2
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%4 = insertelement <4 x float> %3, float %f, i32 3
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%5 = insertelement <4 x float> undef, float %f, i32 0
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%6 = insertelement <4 x float> %5, float %f, i32 1
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%7 = insertelement <4 x float> %6, float %f, i32 2
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%8 = insertelement <4 x float> %7, float %f, i32 3
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%9 = shufflevector <4 x float> %4, <4 x float> %8, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
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ret <8 x float> %9
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}
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; CHECK-LABEL: splat_concat3
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastsd
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; CHECK-NEXT: ret
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define <4 x double> @splat_concat3(double %d) {
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%1 = insertelement <2 x double> undef, double %d, i32 0
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%2 = insertelement <2 x double> %1, double %d, i32 1
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%3 = shufflevector <2 x double> %2, <2 x double> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>
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ret <4 x double> %3
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}
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; CHECK-LABEL: splat_concat4
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; CHECK-NOT: vinsertf128
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; CHECK: vbroadcastsd
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; CHECK-NEXT: ret
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define <4 x double> @splat_concat4(double %d) {
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%1 = insertelement <2 x double> undef, double %d, i32 0
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%2 = insertelement <2 x double> %1, double %d, i32 1
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%3 = insertelement <2 x double> undef, double %d, i32 0
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%4 = insertelement <2 x double> %3, double %d, i32 1
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%5 = shufflevector <2 x double> %2, <2 x double> %4, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
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ret <4 x double> %5
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}
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