From a68e90c36e6a53fb1889b608f44d6244a36b3e97 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 15 Nov 2011 20:29:42 +0000 Subject: [PATCH] ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. Yet more of rdar://10435076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrVFP.td | 11 +++++++++++ test/MC/ARM/simple-fp-encoding.s | 10 ++++++++++ 2 files changed, 21 insertions(+) diff --git a/lib/Target/ARM/ARMInstrVFP.td b/lib/Target/ARM/ARMInstrVFP.td index 81a4a55b54a..27e185f3ca3 100644 --- a/lib/Target/ARM/ARMInstrVFP.td +++ b/lib/Target/ARM/ARMInstrVFP.td @@ -1178,3 +1178,14 @@ def : VFP2InstAlias<"vmul${p}.f64 $Dn, $Dm", (VMULD DPR:$Dn, DPR:$Dn, DPR:$Dm, pred:$p)>; def : VFP2InstAlias<"vmul${p}.f32 $Sn, $Sm", (VMULS SPR:$Sn, SPR:$Sn, SPR:$Sm, pred:$p)>; + +// VMOV can accept optional .f32/.f64 suffix. +def : VFP2InstAlias<"vmov${p}.f32 $Rt, $Sn", + (VMOVRS GPR:$Rt, SPR:$Sn, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.f32 $Sn, $Rt", + (VMOVSR SPR:$Sn, GPR:$Rt, pred:$p)>; + +def : VFP2InstAlias<"vmov${p}.f64 $Rt, $Rt2, $Dn", + (VMOVRRD GPR:$Rt, GPR:$Rt2, DPR:$Dn, pred:$p)>; +def : VFP2InstAlias<"vmov${p}.f64 $Dn, $Rt, $Rt2", + (VMOVDRR DPR:$Dn, GPR:$Rt, GPR:$Rt2, pred:$p)>; diff --git a/test/MC/ARM/simple-fp-encoding.s b/test/MC/ARM/simple-fp-encoding.s index fc0c7c992e5..58abe8894be 100644 --- a/test/MC/ARM/simple-fp-encoding.s +++ b/test/MC/ARM/simple-fp-encoding.s @@ -133,6 +133,16 @@ vmovne s0, r0 vmoveq s0, r1 + vmov.f32 r1, s2 + vmov.f32 s4, r3 + vmov.f64 r1, r5, d2 + vmov.f64 d4, r3, r9 + +@ CHECK: vmov r1, s2 @ encoding: [0x10,0x1a,0x11,0xee] +@ CHECK: vmov s4, r3 @ encoding: [0x10,0x3a,0x02,0xee] +@ CHECK: vmov r1, r5, d2 @ encoding: [0x12,0x1b,0x55,0xec] +@ CHECK: vmov d4, r3, r9 @ encoding: [0x14,0x3b,0x49,0xec] + @ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee] vmrs r0, fpscr @ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]