mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
Added a table for intrinsics on X86.
It should remove dosens of lines in handling instrinsics (in a huge switch) and give an easy way to add new intrinsics. I did not completed to move al intrnsics to the table, I'll do this in the upcomming commits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@215826 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
7a0201c6a6
commit
a73ac1f463
@ -49,6 +49,7 @@
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Target/TargetOptions.h"
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#include "X86IntrinsicsInfo.h"
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#include <bitset>
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#include <numeric>
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#include <cctype>
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@ -14477,110 +14478,43 @@ static unsigned getOpcodeForFMAIntrinsic(unsigned IntNo) {
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static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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SDLoc dl(Op);
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InitIntrinsicsWithoutChain();
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unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
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switch (IntNo) {
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default: return SDValue(); // Don't custom lower most intrinsics.
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// Comparison intrinsics.
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case Intrinsic::x86_sse_comieq_ss:
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case Intrinsic::x86_sse_comilt_ss:
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case Intrinsic::x86_sse_comile_ss:
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case Intrinsic::x86_sse_comigt_ss:
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case Intrinsic::x86_sse_comige_ss:
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case Intrinsic::x86_sse_comineq_ss:
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case Intrinsic::x86_sse_ucomieq_ss:
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case Intrinsic::x86_sse_ucomilt_ss:
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case Intrinsic::x86_sse_ucomile_ss:
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case Intrinsic::x86_sse_ucomigt_ss:
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case Intrinsic::x86_sse_ucomige_ss:
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case Intrinsic::x86_sse_ucomineq_ss:
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case Intrinsic::x86_sse2_comieq_sd:
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case Intrinsic::x86_sse2_comilt_sd:
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case Intrinsic::x86_sse2_comile_sd:
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case Intrinsic::x86_sse2_comigt_sd:
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case Intrinsic::x86_sse2_comige_sd:
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case Intrinsic::x86_sse2_comineq_sd:
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case Intrinsic::x86_sse2_ucomieq_sd:
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case Intrinsic::x86_sse2_ucomilt_sd:
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case Intrinsic::x86_sse2_ucomile_sd:
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case Intrinsic::x86_sse2_ucomigt_sd:
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case Intrinsic::x86_sse2_ucomige_sd:
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case Intrinsic::x86_sse2_ucomineq_sd: {
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unsigned Opc;
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ISD::CondCode CC;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse_comieq_ss:
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case Intrinsic::x86_sse2_comieq_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETEQ;
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break;
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case Intrinsic::x86_sse_comilt_ss:
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case Intrinsic::x86_sse2_comilt_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETLT;
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break;
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case Intrinsic::x86_sse_comile_ss:
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case Intrinsic::x86_sse2_comile_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETLE;
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break;
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case Intrinsic::x86_sse_comigt_ss:
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case Intrinsic::x86_sse2_comigt_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETGT;
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break;
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case Intrinsic::x86_sse_comige_ss:
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case Intrinsic::x86_sse2_comige_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETGE;
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break;
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case Intrinsic::x86_sse_comineq_ss:
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case Intrinsic::x86_sse2_comineq_sd:
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Opc = X86ISD::COMI;
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CC = ISD::SETNE;
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break;
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case Intrinsic::x86_sse_ucomieq_ss:
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case Intrinsic::x86_sse2_ucomieq_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETEQ;
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break;
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case Intrinsic::x86_sse_ucomilt_ss:
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case Intrinsic::x86_sse2_ucomilt_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETLT;
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break;
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case Intrinsic::x86_sse_ucomile_ss:
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case Intrinsic::x86_sse2_ucomile_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETLE;
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break;
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case Intrinsic::x86_sse_ucomigt_ss:
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case Intrinsic::x86_sse2_ucomigt_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETGT;
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break;
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case Intrinsic::x86_sse_ucomige_ss:
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case Intrinsic::x86_sse2_ucomige_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETGE;
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break;
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case Intrinsic::x86_sse_ucomineq_ss:
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case Intrinsic::x86_sse2_ucomineq_sd:
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Opc = X86ISD::UCOMI;
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CC = ISD::SETNE;
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const IntrinsicData* IntrData = GetIntrinsicWithoutChain(IntNo);
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if (IntrData) {
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switch(IntrData->Type) {
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case INTR_TYPE_1OP:
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1));
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case INTR_TYPE_2OP:
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
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Op.getOperand(2));
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case INTR_TYPE_3OP:
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return DAG.getNode(IntrData->Opc0, dl, Op.getValueType(), Op.getOperand(1),
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Op.getOperand(2), Op.getOperand(3));
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case COMI: { // Comparison intrinsics
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ISD::CondCode CC = (ISD::CondCode)IntrData->Opc1;
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
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assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
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SDValue Cond = DAG.getNode(IntrData->Opc0, dl, MVT::i32, LHS, RHS);
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SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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}
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case VSHIFT:
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return getTargetVShiftNode(IntrData->Opc0, dl, Op.getSimpleValueType(),
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Op.getOperand(1), Op.getOperand(2), DAG);
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default:
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break;
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}
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SDValue LHS = Op.getOperand(1);
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SDValue RHS = Op.getOperand(2);
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unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG);
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assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!");
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SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS);
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SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
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DAG.getConstant(X86CC, MVT::i8), Cond);
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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}
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switch (IntNo) {
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default: return SDValue(); // Don't custom lower most intrinsics.
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// Arithmetic intrinsics.
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case Intrinsic::x86_sse2_pmulu_dq:
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case Intrinsic::x86_avx2_pmulu_dq:
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@ -14602,128 +14536,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::MULHS, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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// SSE2/AVX2 sub with unsigned saturation intrinsics
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case Intrinsic::x86_sse2_psubus_b:
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case Intrinsic::x86_sse2_psubus_w:
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case Intrinsic::x86_avx2_psubus_b:
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case Intrinsic::x86_avx2_psubus_w:
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return DAG.getNode(X86ISD::SUBUS, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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// SSE3/AVX horizontal add/sub intrinsics
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case Intrinsic::x86_sse3_hadd_ps:
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case Intrinsic::x86_sse3_hadd_pd:
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case Intrinsic::x86_avx_hadd_ps_256:
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case Intrinsic::x86_avx_hadd_pd_256:
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case Intrinsic::x86_sse3_hsub_ps:
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case Intrinsic::x86_sse3_hsub_pd:
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case Intrinsic::x86_avx_hsub_ps_256:
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case Intrinsic::x86_avx_hsub_pd_256:
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case Intrinsic::x86_ssse3_phadd_w_128:
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case Intrinsic::x86_ssse3_phadd_d_128:
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case Intrinsic::x86_avx2_phadd_w:
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case Intrinsic::x86_avx2_phadd_d:
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case Intrinsic::x86_ssse3_phsub_w_128:
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case Intrinsic::x86_ssse3_phsub_d_128:
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case Intrinsic::x86_avx2_phsub_w:
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case Intrinsic::x86_avx2_phsub_d: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse3_hadd_ps:
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case Intrinsic::x86_sse3_hadd_pd:
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case Intrinsic::x86_avx_hadd_ps_256:
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case Intrinsic::x86_avx_hadd_pd_256:
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Opcode = X86ISD::FHADD;
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break;
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case Intrinsic::x86_sse3_hsub_ps:
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case Intrinsic::x86_sse3_hsub_pd:
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case Intrinsic::x86_avx_hsub_ps_256:
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case Intrinsic::x86_avx_hsub_pd_256:
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Opcode = X86ISD::FHSUB;
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break;
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case Intrinsic::x86_ssse3_phadd_w_128:
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case Intrinsic::x86_ssse3_phadd_d_128:
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case Intrinsic::x86_avx2_phadd_w:
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case Intrinsic::x86_avx2_phadd_d:
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Opcode = X86ISD::HADD;
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break;
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case Intrinsic::x86_ssse3_phsub_w_128:
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case Intrinsic::x86_ssse3_phsub_d_128:
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case Intrinsic::x86_avx2_phsub_w:
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case Intrinsic::x86_avx2_phsub_d:
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Opcode = X86ISD::HSUB;
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break;
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}
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return DAG.getNode(Opcode, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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}
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// SSE2/SSE41/AVX2 integer max/min intrinsics.
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case Intrinsic::x86_sse2_pmaxu_b:
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case Intrinsic::x86_sse41_pmaxuw:
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case Intrinsic::x86_sse41_pmaxud:
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case Intrinsic::x86_avx2_pmaxu_b:
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case Intrinsic::x86_avx2_pmaxu_w:
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case Intrinsic::x86_avx2_pmaxu_d:
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case Intrinsic::x86_sse2_pminu_b:
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case Intrinsic::x86_sse41_pminuw:
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case Intrinsic::x86_sse41_pminud:
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case Intrinsic::x86_avx2_pminu_b:
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case Intrinsic::x86_avx2_pminu_w:
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case Intrinsic::x86_avx2_pminu_d:
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case Intrinsic::x86_sse41_pmaxsb:
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case Intrinsic::x86_sse2_pmaxs_w:
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case Intrinsic::x86_sse41_pmaxsd:
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case Intrinsic::x86_avx2_pmaxs_b:
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case Intrinsic::x86_avx2_pmaxs_w:
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case Intrinsic::x86_avx2_pmaxs_d:
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case Intrinsic::x86_sse41_pminsb:
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case Intrinsic::x86_sse2_pmins_w:
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case Intrinsic::x86_sse41_pminsd:
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case Intrinsic::x86_avx2_pmins_b:
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case Intrinsic::x86_avx2_pmins_w:
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case Intrinsic::x86_avx2_pmins_d: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse2_pmaxu_b:
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case Intrinsic::x86_sse41_pmaxuw:
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case Intrinsic::x86_sse41_pmaxud:
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case Intrinsic::x86_avx2_pmaxu_b:
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case Intrinsic::x86_avx2_pmaxu_w:
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case Intrinsic::x86_avx2_pmaxu_d:
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Opcode = X86ISD::UMAX;
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break;
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case Intrinsic::x86_sse2_pminu_b:
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case Intrinsic::x86_sse41_pminuw:
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case Intrinsic::x86_sse41_pminud:
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case Intrinsic::x86_avx2_pminu_b:
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case Intrinsic::x86_avx2_pminu_w:
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case Intrinsic::x86_avx2_pminu_d:
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Opcode = X86ISD::UMIN;
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break;
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case Intrinsic::x86_sse41_pmaxsb:
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case Intrinsic::x86_sse2_pmaxs_w:
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case Intrinsic::x86_sse41_pmaxsd:
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case Intrinsic::x86_avx2_pmaxs_b:
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case Intrinsic::x86_avx2_pmaxs_w:
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case Intrinsic::x86_avx2_pmaxs_d:
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Opcode = X86ISD::SMAX;
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break;
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case Intrinsic::x86_sse41_pminsb:
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case Intrinsic::x86_sse2_pmins_w:
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case Intrinsic::x86_sse41_pminsd:
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case Intrinsic::x86_avx2_pmins_b:
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case Intrinsic::x86_avx2_pmins_w:
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case Intrinsic::x86_avx2_pmins_d:
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Opcode = X86ISD::SMIN;
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break;
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}
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return DAG.getNode(Opcode, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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}
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// SSE/SSE2/AVX floating point max/min intrinsics.
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case Intrinsic::x86_sse_max_ps:
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case Intrinsic::x86_sse2_max_pd:
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@ -14828,17 +14640,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::PSIGN, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2));
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case Intrinsic::x86_sse41_insertps:
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return DAG.getNode(X86ISD::INSERTPS, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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case Intrinsic::x86_avx_vperm2f128_ps_256:
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case Intrinsic::x86_avx_vperm2f128_pd_256:
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case Intrinsic::x86_avx_vperm2f128_si_256:
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case Intrinsic::x86_avx2_vperm2i128:
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return DAG.getNode(X86ISD::VPERM2X128, dl, Op.getValueType(),
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Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
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case Intrinsic::x86_avx2_permd:
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case Intrinsic::x86_avx2_permps:
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// Operands intentionally swapped. Mask is last operand to intrinsic,
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@ -14846,12 +14647,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(X86ISD::VPERMV, dl, Op.getValueType(),
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Op.getOperand(2), Op.getOperand(1));
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case Intrinsic::x86_sse_sqrt_ps:
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case Intrinsic::x86_sse2_sqrt_pd:
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case Intrinsic::x86_avx_sqrt_ps_256:
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case Intrinsic::x86_avx_sqrt_pd_256:
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return DAG.getNode(ISD::FSQRT, dl, Op.getValueType(), Op.getOperand(1));
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case Intrinsic::x86_avx512_mask_valign_q_512:
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case Intrinsic::x86_avx512_mask_valign_d_512:
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// Vector source operands are swapped.
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@ -14937,100 +14732,6 @@ static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC);
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}
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// SSE/AVX shift intrinsics
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_avx2_psll_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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case Intrinsic::x86_sse2_psrl_w:
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case Intrinsic::x86_sse2_psrl_d:
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case Intrinsic::x86_sse2_psrl_q:
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case Intrinsic::x86_avx2_psrl_w:
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case Intrinsic::x86_avx2_psrl_d:
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case Intrinsic::x86_avx2_psrl_q:
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case Intrinsic::x86_sse2_psra_w:
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case Intrinsic::x86_sse2_psra_d:
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case Intrinsic::x86_avx2_psra_w:
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case Intrinsic::x86_avx2_psra_d: {
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unsigned Opcode;
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switch (IntNo) {
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default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
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case Intrinsic::x86_sse2_psll_w:
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case Intrinsic::x86_sse2_psll_d:
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case Intrinsic::x86_sse2_psll_q:
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case Intrinsic::x86_avx2_psll_w:
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case Intrinsic::x86_avx2_psll_d:
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case Intrinsic::x86_avx2_psll_q:
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Opcode = X86ISD::VSHL;
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break;
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case Intrinsic::x86_sse2_psrl_w:
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case Intrinsic::x86_sse2_psrl_d:
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case Intrinsic::x86_sse2_psrl_q:
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case Intrinsic::x86_avx2_psrl_w:
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case Intrinsic::x86_avx2_psrl_d:
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case Intrinsic::x86_avx2_psrl_q:
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Opcode = X86ISD::VSRL;
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break;
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||||
case Intrinsic::x86_sse2_psra_w:
|
||||
case Intrinsic::x86_sse2_psra_d:
|
||||
case Intrinsic::x86_avx2_psra_w:
|
||||
case Intrinsic::x86_avx2_psra_d:
|
||||
Opcode = X86ISD::VSRA;
|
||||
break;
|
||||
}
|
||||
return DAG.getNode(Opcode, dl, Op.getValueType(),
|
||||
Op.getOperand(1), Op.getOperand(2));
|
||||
}
|
||||
|
||||
// SSE/AVX immediate shift intrinsics
|
||||
case Intrinsic::x86_sse2_pslli_w:
|
||||
case Intrinsic::x86_sse2_pslli_d:
|
||||
case Intrinsic::x86_sse2_pslli_q:
|
||||
case Intrinsic::x86_avx2_pslli_w:
|
||||
case Intrinsic::x86_avx2_pslli_d:
|
||||
case Intrinsic::x86_avx2_pslli_q:
|
||||
case Intrinsic::x86_sse2_psrli_w:
|
||||
case Intrinsic::x86_sse2_psrli_d:
|
||||
case Intrinsic::x86_sse2_psrli_q:
|
||||
case Intrinsic::x86_avx2_psrli_w:
|
||||
case Intrinsic::x86_avx2_psrli_d:
|
||||
case Intrinsic::x86_avx2_psrli_q:
|
||||
case Intrinsic::x86_sse2_psrai_w:
|
||||
case Intrinsic::x86_sse2_psrai_d:
|
||||
case Intrinsic::x86_avx2_psrai_w:
|
||||
case Intrinsic::x86_avx2_psrai_d: {
|
||||
unsigned Opcode;
|
||||
switch (IntNo) {
|
||||
default: llvm_unreachable("Impossible intrinsic"); // Can't reach here.
|
||||
case Intrinsic::x86_sse2_pslli_w:
|
||||
case Intrinsic::x86_sse2_pslli_d:
|
||||
case Intrinsic::x86_sse2_pslli_q:
|
||||
case Intrinsic::x86_avx2_pslli_w:
|
||||
case Intrinsic::x86_avx2_pslli_d:
|
||||
case Intrinsic::x86_avx2_pslli_q:
|
||||
Opcode = X86ISD::VSHLI;
|
||||
break;
|
||||
case Intrinsic::x86_sse2_psrli_w:
|
||||
case Intrinsic::x86_sse2_psrli_d:
|
||||
case Intrinsic::x86_sse2_psrli_q:
|
||||
case Intrinsic::x86_avx2_psrli_w:
|
||||
case Intrinsic::x86_avx2_psrli_d:
|
||||
case Intrinsic::x86_avx2_psrli_q:
|
||||
Opcode = X86ISD::VSRLI;
|
||||
break;
|
||||
case Intrinsic::x86_sse2_psrai_w:
|
||||
case Intrinsic::x86_sse2_psrai_d:
|
||||
case Intrinsic::x86_avx2_psrai_w:
|
||||
case Intrinsic::x86_avx2_psrai_d:
|
||||
Opcode = X86ISD::VSRAI;
|
||||
break;
|
||||
}
|
||||
return getTargetVShiftNode(Opcode, dl, Op.getSimpleValueType(),
|
||||
Op.getOperand(1), Op.getOperand(2), DAG);
|
||||
}
|
||||
|
||||
case Intrinsic::x86_sse42_pcmpistria128:
|
||||
case Intrinsic::x86_sse42_pcmpestria128:
|
||||
case Intrinsic::x86_sse42_pcmpistric128:
|
||||
@ -15342,122 +15043,26 @@ static SDValue LowerREADCYCLECOUNTER(SDValue Op, const X86Subtarget *Subtarget,
|
||||
return DAG.getMergeValues(Results, DL);
|
||||
}
|
||||
|
||||
enum IntrinsicType {
|
||||
GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST
|
||||
};
|
||||
|
||||
struct IntrinsicData {
|
||||
IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
|
||||
:Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
|
||||
IntrinsicType Type;
|
||||
unsigned Opc0;
|
||||
unsigned Opc1;
|
||||
};
|
||||
|
||||
std::map < unsigned, IntrinsicData> IntrMap;
|
||||
static void InitIntinsicsMap() {
|
||||
static bool Initialized = false;
|
||||
if (Initialized)
|
||||
return;
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
|
||||
IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qps_512,
|
||||
IntrinsicData(GATHER, X86::VGATHERQPSZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpd_512,
|
||||
IntrinsicData(GATHER, X86::VGATHERQPDZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpd_512,
|
||||
IntrinsicData(GATHER, X86::VGATHERDPDZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dps_512,
|
||||
IntrinsicData(GATHER, X86::VGATHERDPSZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpi_512,
|
||||
IntrinsicData(GATHER, X86::VPGATHERQDZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_qpq_512,
|
||||
IntrinsicData(GATHER, X86::VPGATHERQQZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpi_512,
|
||||
IntrinsicData(GATHER, X86::VPGATHERDDZrm, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gather_dpq_512,
|
||||
IntrinsicData(GATHER, X86::VPGATHERDQZrm, 0)));
|
||||
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qps_512,
|
||||
IntrinsicData(SCATTER, X86::VSCATTERQPSZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpd_512,
|
||||
IntrinsicData(SCATTER, X86::VSCATTERQPDZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpd_512,
|
||||
IntrinsicData(SCATTER, X86::VSCATTERDPDZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dps_512,
|
||||
IntrinsicData(SCATTER, X86::VSCATTERDPSZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpi_512,
|
||||
IntrinsicData(SCATTER, X86::VPSCATTERQDZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_qpq_512,
|
||||
IntrinsicData(SCATTER, X86::VPSCATTERQQZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpi_512,
|
||||
IntrinsicData(SCATTER, X86::VPSCATTERDDZmr, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatter_dpq_512,
|
||||
IntrinsicData(SCATTER, X86::VPSCATTERDQZmr, 0)));
|
||||
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qps_512,
|
||||
IntrinsicData(PREFETCH, X86::VGATHERPF0QPSm,
|
||||
X86::VGATHERPF1QPSm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_qpd_512,
|
||||
IntrinsicData(PREFETCH, X86::VGATHERPF0QPDm,
|
||||
X86::VGATHERPF1QPDm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dpd_512,
|
||||
IntrinsicData(PREFETCH, X86::VGATHERPF0DPDm,
|
||||
X86::VGATHERPF1DPDm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_gatherpf_dps_512,
|
||||
IntrinsicData(PREFETCH, X86::VGATHERPF0DPSm,
|
||||
X86::VGATHERPF1DPSm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qps_512,
|
||||
IntrinsicData(PREFETCH, X86::VSCATTERPF0QPSm,
|
||||
X86::VSCATTERPF1QPSm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_qpd_512,
|
||||
IntrinsicData(PREFETCH, X86::VSCATTERPF0QPDm,
|
||||
X86::VSCATTERPF1QPDm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dpd_512,
|
||||
IntrinsicData(PREFETCH, X86::VSCATTERPF0DPDm,
|
||||
X86::VSCATTERPF1DPDm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_avx512_scatterpf_dps_512,
|
||||
IntrinsicData(PREFETCH, X86::VSCATTERPF0DPSm,
|
||||
X86::VSCATTERPF1DPSm)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_16,
|
||||
IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_32,
|
||||
IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdrand_64,
|
||||
IntrinsicData(RDRAND, X86ISD::RDRAND, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_16,
|
||||
IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_32,
|
||||
IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdseed_64,
|
||||
IntrinsicData(RDSEED, X86ISD::RDSEED, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_xtest,
|
||||
IntrinsicData(XTEST, X86ISD::XTEST, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdtsc,
|
||||
IntrinsicData(RDTSC, X86ISD::RDTSC_DAG, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdtscp,
|
||||
IntrinsicData(RDTSC, X86ISD::RDTSCP_DAG, 0)));
|
||||
IntrMap.insert(std::make_pair(Intrinsic::x86_rdpmc,
|
||||
IntrinsicData(RDPMC, X86ISD::RDPMC_DAG, 0)));
|
||||
Initialized = true;
|
||||
}
|
||||
|
||||
static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SelectionDAG &DAG) {
|
||||
InitIntinsicsMap();
|
||||
InitIntrinsicsWithChain();
|
||||
unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
||||
std::map < unsigned, IntrinsicData>::const_iterator itr = IntrMap.find(IntNo);
|
||||
if (itr == IntrMap.end())
|
||||
|
||||
const IntrinsicData* IntrData = GetIntrinsicWithChain(IntNo);
|
||||
if (!IntrData)
|
||||
return SDValue();
|
||||
|
||||
SDLoc dl(Op);
|
||||
IntrinsicData Intr = itr->second;
|
||||
switch(Intr.Type) {
|
||||
switch(IntrData->Type) {
|
||||
default:
|
||||
llvm_unreachable("Unknown Intrinsic Type");
|
||||
break;
|
||||
case RDSEED:
|
||||
case RDRAND: {
|
||||
// Emit the node with the right value type.
|
||||
SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Glue, MVT::Other);
|
||||
SDValue Result = DAG.getNode(Intr.Opc0, dl, VTs, Op.getOperand(0));
|
||||
SDValue Result = DAG.getNode(IntrData->Opc0, dl, VTs, Op.getOperand(0));
|
||||
|
||||
// If the value returned by RDRAND/RDSEED was valid (CF=1), return 1.
|
||||
// Otherwise return the value from Rand, which is always 0, casted to i32.
|
||||
@ -15481,7 +15086,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SDValue Index = Op.getOperand(4);
|
||||
SDValue Mask = Op.getOperand(5);
|
||||
SDValue Scale = Op.getOperand(6);
|
||||
return getGatherNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
|
||||
return getGatherNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain,
|
||||
Subtarget);
|
||||
}
|
||||
case SCATTER: {
|
||||
@ -15492,7 +15097,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
SDValue Index = Op.getOperand(4);
|
||||
SDValue Src = Op.getOperand(5);
|
||||
SDValue Scale = Op.getOperand(6);
|
||||
return getScatterNode(Intr.Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
|
||||
return getScatterNode(IntrData->Opc0, Op, DAG, Src, Mask, Base, Index, Scale, Chain);
|
||||
}
|
||||
case PREFETCH: {
|
||||
SDValue Hint = Op.getOperand(6);
|
||||
@ -15500,7 +15105,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
if (dyn_cast<ConstantSDNode> (Hint) == nullptr ||
|
||||
(HintVal = dyn_cast<ConstantSDNode> (Hint)->getZExtValue()) > 1)
|
||||
llvm_unreachable("Wrong prefetch hint in intrinsic: should be 0 or 1");
|
||||
unsigned Opcode = (HintVal ? Intr.Opc1 : Intr.Opc0);
|
||||
unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
|
||||
SDValue Chain = Op.getOperand(0);
|
||||
SDValue Mask = Op.getOperand(2);
|
||||
SDValue Index = Op.getOperand(3);
|
||||
@ -15511,7 +15116,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
// Read Time Stamp Counter (RDTSC) and Processor ID (RDTSCP).
|
||||
case RDTSC: {
|
||||
SmallVector<SDValue, 2> Results;
|
||||
getReadTimeStampCounter(Op.getNode(), dl, Intr.Opc0, DAG, Subtarget, Results);
|
||||
getReadTimeStampCounter(Op.getNode(), dl, IntrData->Opc0, DAG, Subtarget, Results);
|
||||
return DAG.getMergeValues(Results, dl);
|
||||
}
|
||||
// Read Performance Monitoring Counters.
|
||||
@ -15532,7 +15137,7 @@ static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget *Subtarget,
|
||||
Ret, SDValue(InTrans.getNode(), 1));
|
||||
}
|
||||
}
|
||||
llvm_unreachable("Unknown Intrinsic Type");
|
||||
|
||||
}
|
||||
|
||||
SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op,
|
||||
|
||||
235
lib/Target/X86/X86IntrinsicsInfo.h
Normal file
235
lib/Target/X86/X86IntrinsicsInfo.h
Normal file
@ -0,0 +1,235 @@
|
||||
//===-- X86IntinsicsInfo.h - X86 Instrinsics ------------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the details for lowering X86 intrinsics
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef LLVM_LIB_TARGET_X86_X86INTRINSICSINFO_H
|
||||
#define LLVM_LIB_TARGET_X86_X86INTRINSICSINFO_H
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
enum IntrinsicType {
|
||||
GATHER, SCATTER, PREFETCH, RDSEED, RDRAND, RDPMC, RDTSC, XTEST,
|
||||
INTR_TYPE_1OP, INTR_TYPE_2OP, INTR_TYPE_3OP, VSHIFT,
|
||||
COMI
|
||||
};
|
||||
|
||||
struct IntrinsicData {
|
||||
IntrinsicData(IntrinsicType IType, unsigned IOpc0, unsigned IOpc1)
|
||||
:Type(IType), Opc0(IOpc0), Opc1(IOpc1) {}
|
||||
IntrinsicType Type;
|
||||
unsigned Opc0;
|
||||
unsigned Opc1;
|
||||
};
|
||||
|
||||
#define INTRINSIC_WITH_CHAIN(id, type, op0, op1) \
|
||||
IntrWithChainMap.insert(std::make_pair(Intrinsic::id, \
|
||||
IntrinsicData(type, op0, op1)))
|
||||
|
||||
|
||||
std::map < unsigned, IntrinsicData> IntrWithChainMap;
|
||||
void InitIntrinsicsWithChain() {
|
||||
static bool Initialized = false;
|
||||
if (Initialized)
|
||||
return;
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_qps_512, GATHER, X86::VGATHERQPSZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_qpd_512, GATHER, X86::VGATHERQPDZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_dps_512, GATHER, X86::VGATHERDPSZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_dpd_512, GATHER, X86::VGATHERDPDZrm, 0);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_qpi_512, GATHER, X86::VPGATHERQDZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_qpq_512, GATHER, X86::VPGATHERQQZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_dpi_512, GATHER, X86::VPGATHERDDZrm, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gather_dpq_512, GATHER, X86::VPGATHERDQZrm, 0);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_qps_512, SCATTER, X86::VSCATTERQPSZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_qpd_512, SCATTER, X86::VSCATTERQPDZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_dps_512, SCATTER, X86::VSCATTERDPSZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_dpd_512, SCATTER, X86::VSCATTERDPDZmr, 0);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_qpi_512, SCATTER, X86::VPSCATTERQDZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_qpq_512, SCATTER, X86::VPSCATTERQQZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_dpi_512, SCATTER, X86::VPSCATTERDDZmr, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatter_dpq_512, SCATTER, X86::VPSCATTERDQZmr, 0);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gatherpf_qps_512, PREFETCH, X86::VGATHERPF0QPSm, X86::VGATHERPF1QPSm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gatherpf_qpd_512, PREFETCH, X86::VGATHERPF0QPDm, X86::VGATHERPF1QPDm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gatherpf_dps_512, PREFETCH, X86::VGATHERPF0DPSm, X86::VGATHERPF1DPSm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_gatherpf_dpd_512, PREFETCH, X86::VGATHERPF0DPDm, X86::VGATHERPF1DPDm);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatterpf_qps_512, PREFETCH, X86::VSCATTERPF0QPSm, X86::VSCATTERPF1QPSm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatterpf_qpd_512, PREFETCH, X86::VSCATTERPF0QPDm, X86::VSCATTERPF1QPDm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatterpf_dps_512, PREFETCH, X86::VSCATTERPF0DPSm, X86::VSCATTERPF1DPSm);
|
||||
INTRINSIC_WITH_CHAIN(x86_avx512_scatterpf_dpd_512, PREFETCH, X86::VSCATTERPF0DPDm, X86::VSCATTERPF1DPDm);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_rdrand_16, RDRAND, X86ISD::RDRAND, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdrand_32, RDRAND, X86ISD::RDRAND, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdrand_64, RDRAND, X86ISD::RDRAND, 0);
|
||||
|
||||
INTRINSIC_WITH_CHAIN(x86_rdseed_16, RDSEED, X86ISD::RDSEED, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdseed_32, RDSEED, X86ISD::RDSEED, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdseed_64, RDSEED, X86ISD::RDSEED, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_xtest, XTEST, X86ISD::XTEST, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdtsc, RDTSC, X86ISD::RDTSC_DAG, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdtscp, RDTSC, X86ISD::RDTSCP_DAG, 0);
|
||||
INTRINSIC_WITH_CHAIN(x86_rdpmc, RDPMC, X86ISD::RDPMC_DAG, 0);
|
||||
Initialized = true;
|
||||
}
|
||||
|
||||
const IntrinsicData* GetIntrinsicWithChain(unsigned IntNo) {
|
||||
std::map < unsigned, IntrinsicData>::const_iterator itr =
|
||||
IntrWithChainMap.find(IntNo);
|
||||
if (itr == IntrWithChainMap.end())
|
||||
return NULL;
|
||||
return &(itr->second);
|
||||
}
|
||||
|
||||
#define INTRINSIC_WO_CHAIN(id, type, op0, op1) \
|
||||
IntrWithoutChainMap.insert(std::make_pair(Intrinsic::id, \
|
||||
IntrinsicData(type, op0, op1)))
|
||||
|
||||
|
||||
std::map < unsigned, IntrinsicData> IntrWithoutChainMap;
|
||||
|
||||
void InitIntrinsicsWithoutChain() {
|
||||
static bool Initialized = false;
|
||||
if (Initialized)
|
||||
return;
|
||||
Initialized = true;
|
||||
INTRINSIC_WO_CHAIN(x86_sse_sqrt_ps, INTR_TYPE_1OP, ISD::FSQRT, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_sqrt_pd, INTR_TYPE_1OP, ISD::FSQRT, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_sqrt_ps_256, INTR_TYPE_1OP, ISD::FSQRT, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_sqrt_pd_256, INTR_TYPE_1OP, ISD::FSQRT, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psubus_b, INTR_TYPE_2OP, X86ISD::SUBUS, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psubus_w, INTR_TYPE_2OP, X86ISD::SUBUS, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psubus_b, INTR_TYPE_2OP, X86ISD::SUBUS, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psubus_w, INTR_TYPE_2OP, X86ISD::SUBUS, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse3_hadd_ps, INTR_TYPE_2OP, X86ISD::FHADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse3_hadd_pd, INTR_TYPE_2OP, X86ISD::FHADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_hadd_ps_256, INTR_TYPE_2OP, X86ISD::FHADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_hadd_pd_256, INTR_TYPE_2OP, X86ISD::FHADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse3_hsub_ps, INTR_TYPE_2OP, X86ISD::FHSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse3_hsub_pd, INTR_TYPE_2OP, X86ISD::FHSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_hsub_ps_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_hsub_pd_256, INTR_TYPE_2OP, X86ISD::FHSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_ssse3_phadd_w_128, INTR_TYPE_2OP, X86ISD::HADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_ssse3_phadd_d_128, INTR_TYPE_2OP, X86ISD::HADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_phadd_w, INTR_TYPE_2OP, X86ISD::HADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_phadd_d, INTR_TYPE_2OP, X86ISD::HADD, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_ssse3_phsub_w_128, INTR_TYPE_2OP, X86ISD::HSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_ssse3_phsub_d_128, INTR_TYPE_2OP, X86ISD::HSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_phsub_w, INTR_TYPE_2OP, X86ISD::HSUB, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_phsub_d, INTR_TYPE_2OP, X86ISD::HSUB, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pmaxu_b, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pmaxuw, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pmaxud, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxu_b, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxu_w, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxu_d, INTR_TYPE_2OP, X86ISD::UMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pminu_b, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pminuw, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pminud, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pminu_b, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pminu_w, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pminu_d, INTR_TYPE_2OP, X86ISD::UMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pmaxsb, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pmaxs_w, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pmaxsd, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxs_b, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxs_w, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmaxs_d, INTR_TYPE_2OP, X86ISD::SMAX, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pminsb, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pmins_w, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_pminsd, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmins_b, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmins_w, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pmins_d, INTR_TYPE_2OP, X86ISD::SMIN, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psll_w, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psll_d, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psll_q, INTR_TYPE_2OP, X86ISD::VSHL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrl_w, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrl_d, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrl_q, INTR_TYPE_2OP, X86ISD::VSRL, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psra_w, INTR_TYPE_2OP, X86ISD::VSRA, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psra_d, INTR_TYPE_2OP, X86ISD::VSRA, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pslli_w, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pslli_d, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_pslli_q, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pslli_w, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pslli_d, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_pslli_q, VSHIFT, X86ISD::VSHLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrli_w, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrli_d, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrli_q, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrli_w, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrli_d, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrli_q, VSHIFT, X86ISD::VSRLI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrai_w, VSHIFT, X86ISD::VSRAI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_psrai_d, VSHIFT, X86ISD::VSRAI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrai_w, VSHIFT, X86ISD::VSRAI, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_psrai_d, VSHIFT, X86ISD::VSRAI, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_avx_vperm2f128_ps_256, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_vperm2f128_pd_256, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx_vperm2f128_si_256, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0);
|
||||
INTRINSIC_WO_CHAIN(x86_avx2_vperm2i128, INTR_TYPE_3OP, X86ISD::VPERM2X128, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse41_insertps, INTR_TYPE_3OP, X86ISD::INSERTPS, 0);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comieq_ss, COMI, X86ISD::COMI, ISD::SETEQ);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comieq_sd, COMI, X86ISD::COMI, ISD::SETEQ);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comilt_ss, COMI, X86ISD::COMI, ISD::SETLT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comilt_sd, COMI, X86ISD::COMI, ISD::SETLT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comile_ss, COMI, X86ISD::COMI, ISD::SETLE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comile_sd, COMI, X86ISD::COMI, ISD::SETLE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comigt_ss, COMI, X86ISD::COMI, ISD::SETGT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comigt_sd, COMI, X86ISD::COMI, ISD::SETGT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comige_ss, COMI, X86ISD::COMI, ISD::SETGE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comige_sd, COMI, X86ISD::COMI, ISD::SETGE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_comineq_ss, COMI, X86ISD::COMI, ISD::SETNE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_comineq_sd,COMI, X86ISD::COMI, ISD::SETNE);
|
||||
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomieq_ss, COMI, X86ISD::UCOMI, ISD::SETEQ);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomieq_sd, COMI, X86ISD::UCOMI, ISD::SETEQ);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomilt_ss, COMI, X86ISD::UCOMI, ISD::SETLT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomilt_sd, COMI, X86ISD::UCOMI, ISD::SETLT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomile_ss, COMI, X86ISD::UCOMI, ISD::SETLE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomile_sd, COMI, X86ISD::UCOMI, ISD::SETLE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomigt_ss, COMI, X86ISD::UCOMI, ISD::SETGT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomigt_sd, COMI, X86ISD::UCOMI, ISD::SETGT);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomige_ss, COMI, X86ISD::UCOMI, ISD::SETGE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomige_sd, COMI, X86ISD::UCOMI, ISD::SETGE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse_ucomineq_ss, COMI, X86ISD::UCOMI, ISD::SETNE);
|
||||
INTRINSIC_WO_CHAIN(x86_sse2_ucomineq_sd,COMI, X86ISD::UCOMI, ISD::SETNE);
|
||||
}
|
||||
|
||||
const IntrinsicData* GetIntrinsicWithoutChain(unsigned IntNo) {
|
||||
std::map < unsigned, IntrinsicData>::const_iterator itr =
|
||||
IntrWithoutChainMap.find(IntNo);
|
||||
if (itr == IntrWithoutChainMap.end())
|
||||
return NULL;
|
||||
return &(itr->second);
|
||||
}
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user