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Revert "[ARM] Add more pattern matching for f16 <-> f64 conversions"

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This change is incorrect since it converts double rounding into single rounding,
which can produce different results. Instead this optimization will be done by
modifying Clang's codegen to not produce double rounding in the first place.

This reverts commit r232954.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232962 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bradley Smith 2015-03-23 16:52:52 +00:00
parent 437c2863f0
commit a75fecc370
2 changed files with 0 additions and 39 deletions
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8
lib/Target/ARM/ARMInstrVFP.td
View File

@ -621,14 +621,6 @@ def : Pat<(f16_to_fp GPR:$a),
def : Pat<(f64 (f16_to_fp GPR:$a)),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
def : Pat<(f64 (fextend (f16_to_fp GPR:$a))),
(VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
def : Pat<(fp_to_f16 (fround (f64 DPR:$a))),
(i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>,
Requires<[HasFPARMv8, HasDPVFP]>;
multiclass vcvt_inst<string opc, bits<2> rm,
SDPatternOperator node = null_frag> {
let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {

31
test/CodeGen/ARM/fp16-64.ll
View File

@ -1,31 +0,0 @@
; RUN: llc -mtriple=arm -mattr=+fp-armv8 < %s | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=V8 %s
; RUN: llc -mtriple=arm -mattr=+vfp3,+d16 < %s | \
; RUN: FileCheck --check-prefix=CHECK --check-prefix=NOV8 %s
declare float @llvm.convert.from.fp16.f32(i16) nounwind readnone
declare i16 @llvm.convert.to.fp16.f32(float) nounwind readnone
define void @vcvt_f64_f16(i16* %x, double* %y) nounwind {
entry:
; CHECK-LABEL: vcvt_f64_f16
%0 = load i16, i16* %x, align 2
%1 = tail call float @llvm.convert.from.fp16.f32(i16 %0)
%conv = fpext float %1 to double
; CHECK-V8: vcvtb.f64.f16
; CHECK-NOV8-NOT: vcvtb.f64.f16
store double %conv, double* %y, align 8
ret void
}
define void @vcvt_f16_f64(i16* %x, double* %y) nounwind {
entry:
; CHECK-LABEL: vcvt_f16_f64
%0 = load double, double* %y, align 8
%conv = fptrunc double %0 to float
; CHECK-V8: vcvtb.f16.f64
; CHECK-NOV8-NOT: vcvtb.f16.f64
%1 = tail call i16 @llvm.convert.to.fp16.f32(float %conv)
store i16 %1, i16* %x, align 2
ret void
}