mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-04 05:17:07 +00:00
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
operands. Some parsing of arm memory operands for preindexing and postindexing forms including with register controled shifts. This is a work in progress. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@83424 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby
@@ -23,6 +23,15 @@ using namespace llvm;
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namespace {
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struct ARMOperand;
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// The shift types for register controlled shifts in arm memory addressing
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enum ShiftType {
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Lsl,
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Lsr,
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Asr,
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Ror,
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Rrx
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};
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class ARMAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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@@ -35,8 +44,31 @@ private:
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(ARMOperand &Op);
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bool ParseMemory(ARMOperand &Op);
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bool ParseShift(enum ShiftType *St, const MCExpr *ShiftAmount);
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bool ParseOperand(ARMOperand &Op);
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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// TODO - For now hacked versions of the next two are in here in this file to
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// allow some parser testing until the table gen versions are implemented.
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/// @name Auto-generated Match Functions
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/// {
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bool MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
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MCInst &Inst);
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/// MatchRegisterName - Match the given string to a register name, or 0 if
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/// there is no match.
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unsigned MatchRegisterName(const StringRef &Name);
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/// }
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public:
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ARMAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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@@ -48,9 +80,380 @@ public:
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} // end anonymous namespace
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namespace {
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/// ARMOperand - Instances of this class represent a parsed ARM machine
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/// instruction.
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struct ARMOperand {
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enum {
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Token,
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Register,
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Memory
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} Kind;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNum;
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} Reg;
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// This is for all forms of ARM address expressions
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struct {
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unsigned BaseRegNum;
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bool OffsetIsReg;
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const MCExpr *Offset; // used when OffsetIsReg is false
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unsigned OffsetRegNum; // used when OffsetIsReg is true
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bool OffsetRegShifted; // only used when OffsetIsReg is true
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enum ShiftType ShiftType; // used when OffsetRegShifted is true
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const MCExpr *ShiftAmount; // used when OffsetRegShifted is true
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bool Preindexed;
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bool Postindexed;
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bool Negative; // only used when OffsetIsReg is true
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bool Writeback;
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} Mem;
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};
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNum;
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}
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bool isToken() const {return Kind == Token; }
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bool isReg() const { return Kind == Register; }
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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static ARMOperand CreateToken(StringRef Str) {
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ARMOperand Res;
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Res.Kind = Token;
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Res.Tok.Data = Str.data();
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Res.Tok.Length = Str.size();
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return Res;
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}
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static ARMOperand CreateReg(unsigned RegNum) {
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ARMOperand Res;
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Res.Kind = Register;
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Res.Reg.RegNum = RegNum;
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return Res;
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}
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static ARMOperand CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
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const MCExpr *Offset, unsigned OffsetRegNum,
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bool OffsetRegShifted, enum ShiftType ShiftType,
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const MCExpr *ShiftAmount, bool Preindexed,
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bool Postindexed, bool Negative, bool Writeback) {
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ARMOperand Res;
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Res.Kind = Memory;
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Res.Mem.BaseRegNum = BaseRegNum;
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Res.Mem.OffsetIsReg = OffsetIsReg;
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Res.Mem.Offset = Offset;
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Res.Mem.OffsetRegNum = OffsetRegNum;
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Res.Mem.OffsetRegShifted = OffsetRegShifted;
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Res.Mem.ShiftType = ShiftType;
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Res.Mem.ShiftAmount = ShiftAmount;
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Res.Mem.Preindexed = Preindexed;
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Res.Mem.Postindexed = Postindexed;
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Res.Mem.Negative = Negative;
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Res.Mem.Writeback = Writeback;
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return Res;
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}
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};
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} // end anonymous namespace.
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// Try to parse a register name. The token must be an Identifier when called,
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// and if it is a register name a Reg operand is created, the token is eaten
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// and false is returned. Else true is returned and no token is eaten.
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// TODO this is likely to change to allow different register types and or to
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// parse for a specific register type.
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bool ARMAsmParser::ParseRegister(ARMOperand &Op) {
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const AsmToken &Tok = getLexer().getTok();
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assert(Tok.is(AsmToken::Identifier) && "Token is not an Identifier");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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unsigned RegNum;
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RegNum = MatchRegisterName(Tok.getString());
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if (RegNum == 0)
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return true;
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Op = ARMOperand::CreateReg(RegNum);
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getLexer().Lex(); // Eat identifier token.
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return false;
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}
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// Try to parse an arm memory expression. It must start with a '[' token.
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// TODO Only preindexing and postindexing addressing are started, unindexed
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// with option, etc are still to do.
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bool ARMAsmParser::ParseMemory(ARMOperand &Op) {
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const AsmToken &LBracTok = getLexer().getTok();
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assert(LBracTok.is(AsmToken::LBrac) && "Token is not an Left Bracket");
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getLexer().Lex(); // Eat left bracket token.
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const AsmToken &BaseRegTok = getLexer().getTok();
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if (BaseRegTok.isNot(AsmToken::Identifier))
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return Error(BaseRegTok.getLoc(), "register expected");
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unsigned BaseRegNum = MatchRegisterName(BaseRegTok.getString());
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if (BaseRegNum == 0)
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return Error(BaseRegTok.getLoc(), "register expected");
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getLexer().Lex(); // Eat identifier token.
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bool Preindexed = false;
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bool Postindexed = false;
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bool OffsetIsReg = false;
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bool Negative = false;
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bool Writeback = false;
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// First look for preindexed address forms:
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// [Rn, +/-Rm]
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// [Rn, #offset]
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// [Rn, +/-Rm, shift]
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// that is after the "[Rn" we now have see if the next token is a comma.
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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Preindexed = true;
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getLexer().Lex(); // Eat comma token.
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const AsmToken &NextTok = getLexer().getTok();
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if (NextTok.is(AsmToken::Plus))
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getLexer().Lex(); // Eat plus token.
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else if (NextTok.is(AsmToken::Minus)) {
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Negative = true;
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getLexer().Lex(); // Eat minus token
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}
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// See if there is a register following the "[Rn," we have so far.
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const AsmToken &OffsetRegTok = getLexer().getTok();
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unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
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bool OffsetRegShifted = false;
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enum ShiftType ShiftType;
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const MCExpr *ShiftAmount;
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const MCExpr *Offset;
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if (OffsetRegNum != 0) {
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OffsetIsReg = true;
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getLexer().Lex(); // Eat identifier token for the offset register.
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// Look for a comma then a shift
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat comma token.
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const AsmToken &Tok = getLexer().getTok();
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if (ParseShift(&ShiftType, ShiftAmount))
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return Error(Tok.getLoc(), "shift expected");
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OffsetRegShifted = true;
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}
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}
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else { // "[Rn," we have so far was not followed by "Rm"
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// Look for #offset following the "[Rn,"
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(Offset))
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return true;
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}
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const AsmToken &RBracTok = getLexer().getTok();
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if (RBracTok.isNot(AsmToken::RBrac))
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return Error(RBracTok.getLoc(), "']' expected");
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getLexer().Lex(); // Eat right bracket token.
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const AsmToken &ExclaimTok = getLexer().getTok();
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if (ExclaimTok.is(AsmToken::Exclaim)) {
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Writeback = true;
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getLexer().Lex(); // Eat exclaim token
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}
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Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback);
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return false;
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}
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// The "[Rn" we have so far was not followed by a comma.
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else if (Tok.is(AsmToken::RBrac)) {
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// This is a post indexing addressing forms:
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// [Rn], #offset
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// [Rn], +/-Rm
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// [Rn], +/-Rm, shift
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// that is a ']' follows after the "[Rn".
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Postindexed = true;
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Writeback = true;
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getLexer().Lex(); // Eat right bracket token.
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const AsmToken &CommaTok = getLexer().getTok();
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if (CommaTok.isNot(AsmToken::Comma))
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return Error(CommaTok.getLoc(), "',' expected");
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getLexer().Lex(); // Eat comma token.
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const AsmToken &NextTok = getLexer().getTok();
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if (NextTok.is(AsmToken::Plus))
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getLexer().Lex(); // Eat plus token.
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else if (NextTok.is(AsmToken::Minus)) {
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Negative = true;
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getLexer().Lex(); // Eat minus token
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}
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// See if there is a register following the "[Rn]," we have so far.
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const AsmToken &OffsetRegTok = getLexer().getTok();
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unsigned OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
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bool OffsetRegShifted = false;
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enum ShiftType ShiftType;
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const MCExpr *ShiftAmount;
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const MCExpr *Offset;
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if (OffsetRegNum != 0) {
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OffsetIsReg = true;
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getLexer().Lex(); // Eat identifier token for the offset register.
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// Look for a comma then a shift
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat comma token.
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const AsmToken &Tok = getLexer().getTok();
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if (ParseShift(&ShiftType, ShiftAmount))
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return Error(Tok.getLoc(), "shift expected");
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OffsetRegShifted = true;
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}
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}
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else { // "[Rn]," we have so far was not followed by "Rm"
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// Look for #offset following the "[Rn],"
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(Offset))
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return true;
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}
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Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
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OffsetRegShifted, ShiftType, ShiftAmount,
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Preindexed, Postindexed, Negative, Writeback);
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return false;
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}
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return true;
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}
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/// ParseShift as one of these two:
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/// ( lsl | lsr | asr | ror ) , # shift_amount
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/// rrx
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/// and returns true if it parses a shift otherwise it returns false.
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bool ARMAsmParser::ParseShift(ShiftType *St, const MCExpr *ShiftAmount) {
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const AsmToken &Tok = getLexer().getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return true;
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const StringRef &ShiftName = Tok.getString();
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if (ShiftName == "lsl" || ShiftName == "LSL")
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*St = Lsl;
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else if (ShiftName == "lsr" || ShiftName == "LSR")
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*St = Lsr;
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else if (ShiftName == "asr" || ShiftName == "ASR")
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*St = Asr;
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else if (ShiftName == "ror" || ShiftName == "ROR")
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*St = Ror;
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else if (ShiftName == "rrx" || ShiftName == "RRX")
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*St = Rrx;
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else
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return true;
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getLexer().Lex(); // Eat shift type token.
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// For all but a Rotate right there must be a '#' and a shift amount
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if (*St != Rrx) {
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// Look for # following the shift type
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const AsmToken &HashTok = getLexer().getTok();
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if (HashTok.isNot(AsmToken::Hash))
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return Error(HashTok.getLoc(), "'#' expected");
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getLexer().Lex(); // Eat hash token.
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if (getParser().ParseExpression(ShiftAmount))
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return true;
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}
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return false;
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}
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// A hack to allow some testing
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unsigned ARMAsmParser::MatchRegisterName(const StringRef &Name) {
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if (Name == "r1")
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return 1;
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else if (Name == "r2")
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return 2;
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else if (Name == "r3")
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return 3;
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return 0;
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}
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// A hack to allow some testing
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bool ARMAsmParser::MatchInstruction(SmallVectorImpl<ARMOperand> &Operands,
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MCInst &Inst) {
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struct ARMOperand Op0 = Operands[0];
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assert(Op0.Kind == ARMOperand::Token && "First operand not a Token");
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const StringRef &Mnemonic = Op0.getToken();
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if (Mnemonic == "add" ||
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Mnemonic == "ldr")
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return false;
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return true;
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}
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// TODO - this is a work in progress
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bool ARMAsmParser::ParseOperand(ARMOperand &Op) {
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switch (getLexer().getKind()) {
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case AsmToken::Identifier:
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if (!ParseRegister(Op))
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return false;
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// TODO parse other operands that start with an identifier
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return true;
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case AsmToken::LBrac:
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if (!ParseMemory(Op))
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return false;
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default:
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return true;
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}
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}
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bool ARMAsmParser::ParseInstruction(const StringRef &Name, MCInst &Inst) {
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SmallVector<ARMOperand, 7> Operands;
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Operands.push_back(ARMOperand::CreateToken(Name));
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SMLoc Loc = getLexer().getTok().getLoc();
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Error(Loc, "ARMAsmParser::ParseInstruction currently unimplemented");
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Read the first operand.
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Operands.push_back(ARMOperand());
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if (ParseOperand(Operands.back()))
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return true;
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while (getLexer().is(AsmToken::Comma)) {
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getLexer().Lex(); // Eat the comma.
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// Parse and remember the operand.
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Operands.push_back(ARMOperand());
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if (ParseOperand(Operands.back()))
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return true;
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}
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}
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if (!MatchInstruction(Operands, Inst))
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return false;
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Error(Loc, "ARMAsmParser::ParseInstruction only partly implemented");
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return true;
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}
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