mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-02 07:11:49 +00:00
trailing whitespace
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117724 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
f0b48f836e
commit
a7c78220c4
@ -20,7 +20,7 @@
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// Some example inputs, for X86:
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// 'addl' (immediate ...) (register ...)
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// 'add' (immediate ...) (memory ...)
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// 'call' '*' %epc
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// 'call' '*' %epc
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//
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// The assembly matcher is responsible for converting this input into a precise
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// machine instruction (i.e., an instruction with a well defined encoding). This
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@ -98,12 +98,12 @@ static std::string FlattenVariants(const std::string &AsmString,
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unsigned N) {
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StringRef Cur = AsmString;
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std::string Res = "";
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for (;;) {
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// Find the start of the next variant string.
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size_t VariantsStart = 0;
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for (size_t e = Cur.size(); VariantsStart != e; ++VariantsStart)
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if (Cur[VariantsStart] == '{' &&
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if (Cur[VariantsStart] == '{' &&
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(VariantsStart == 0 || (Cur[VariantsStart-1] != '$' &&
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Cur[VariantsStart-1] != '\\')))
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break;
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@ -132,16 +132,16 @@ static std::string FlattenVariants(const std::string &AsmString,
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Selection = Selection.split('|').second;
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Res += Selection.split('|').first;
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assert(VariantsEnd != Cur.size() &&
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assert(VariantsEnd != Cur.size() &&
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"Unterminated variants in assembly string!");
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Cur = Cur.substr(VariantsEnd + 1);
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}
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}
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return Res;
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}
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/// TokenizeAsmString - Tokenize a simplified assembly string.
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static void TokenizeAsmString(StringRef AsmString,
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static void TokenizeAsmString(StringRef AsmString,
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SmallVectorImpl<StringRef> &Tokens) {
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unsigned Prev = 0;
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bool InTok = true;
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@ -162,7 +162,7 @@ static void TokenizeAsmString(StringRef AsmString,
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Tokens.push_back(AsmString.substr(i, 1));
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Prev = i + 1;
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break;
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case '\\':
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if (InTok) {
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Tokens.push_back(AsmString.slice(Prev, i));
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@ -217,7 +217,7 @@ static void TokenizeAsmString(StringRef AsmString,
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}
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static bool IsAssemblerInstruction(StringRef Name,
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const CodeGenInstruction &CGI,
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const CodeGenInstruction &CGI,
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const SmallVectorImpl<StringRef> &Tokens) {
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// Ignore "codegen only" instructions.
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if (CGI.TheDef->getValueAsBit("isCodeGenOnly"))
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@ -244,10 +244,10 @@ static bool IsAssemblerInstruction(StringRef Name,
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return false;
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// FIXME: Hack; ignore any instructions with a newline in them.
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if (std::find(CGI.AsmString.begin(),
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if (std::find(CGI.AsmString.begin(),
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CGI.AsmString.end(), '\n') != CGI.AsmString.end())
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return false;
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// Ignore instructions with attributes, these are always fake instructions for
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// simplifying codegen.
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//
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@ -257,12 +257,12 @@ static bool IsAssemblerInstruction(StringRef Name,
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// this implies a constraint we would not honor.
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std::set<std::string> OperandNames;
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for (unsigned i = 1, e = Tokens.size(); i < e; ++i) {
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if (Tokens[i][0] == '$' &&
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std::find(Tokens[i].begin(),
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if (Tokens[i][0] == '$' &&
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std::find(Tokens[i].begin(),
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Tokens[i].end(), ':') != Tokens[i].end()) {
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DEBUG({
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errs() << "warning: '" << Name << "': "
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<< "ignoring instruction; operand with attribute '"
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<< "ignoring instruction; operand with attribute '"
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<< Tokens[i] << "'\n";
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});
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return false;
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@ -361,7 +361,7 @@ public:
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std::set<Record*> Tmp;
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std::insert_iterator< std::set<Record*> > II(Tmp, Tmp.begin());
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std::set_intersection(Registers.begin(), Registers.end(),
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std::set_intersection(Registers.begin(), Registers.end(),
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RHS.Registers.begin(), RHS.Registers.end(),
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II);
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@ -381,11 +381,11 @@ public:
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const ClassInfo *RHSRoot = &RHS;
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while (!RHSRoot->SuperClasses.empty())
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RHSRoot = RHSRoot->SuperClasses.front();
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return Root == RHSRoot;
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}
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/// isSubsetOf - Test whether this class is a subset of \arg RHS;
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/// isSubsetOf - Test whether this class is a subset of \arg RHS;
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bool isSubsetOf(const ClassInfo &RHS) const {
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// This is a subset of RHS if it is the same class...
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if (this == &RHS)
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@ -471,7 +471,7 @@ struct InstructionInfo {
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// The primary comparator is the instruction mnemonic.
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if (Tokens[0] != RHS.Tokens[0])
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return Tokens[0] < RHS.Tokens[0];
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if (Operands.size() != RHS.Operands.size())
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return Operands.size() < RHS.Operands.size();
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@ -507,7 +507,7 @@ struct InstructionInfo {
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if (*Operands[i].Class < *RHS.Operands[i].Class ||
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*RHS.Operands[i].Class < *Operands[i].Class)
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return false;
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// Otherwise, this operand could commute if all operands are equivalent, or
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// there is a pair of operands that compare less than and a pair that
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// compare greater than.
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@ -552,7 +552,7 @@ public:
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/// The classes which are needed for matching.
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std::vector<ClassInfo*> Classes;
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/// The information on the instruction to match.
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std::vector<InstructionInfo*> Instructions;
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@ -599,7 +599,7 @@ private:
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/// BuildRegisterClasses - Build the ClassInfo* instances for register
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/// classes.
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void BuildRegisterClasses(CodeGenTarget &Target,
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void BuildRegisterClasses(CodeGenTarget &Target,
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std::set<std::string> &SingletonRegisterNames);
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/// BuildOperandClasses - Build the ClassInfo* instances for user defined
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@ -646,7 +646,7 @@ void InstructionInfo::dump() {
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static std::string getEnumNameForToken(StringRef Str) {
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std::string Res;
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for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
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switch (*it) {
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case '*': Res += "_STAR_"; break;
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@ -678,7 +678,7 @@ static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) {
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ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
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ClassInfo *&Entry = TokenClasses[Token];
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if (!Entry) {
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Entry = new ClassInfo();
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Entry->Kind = ClassInfo::Token;
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@ -731,7 +731,7 @@ void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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// The register sets used for matching.
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std::set< std::set<Record*> > RegisterSets;
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// Gather the defined sets.
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// Gather the defined sets.
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for (std::vector<CodeGenRegisterClass>::iterator it = RegisterClasses.begin(),
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ie = RegisterClasses.end(); it != ie; ++it)
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RegisterSets.insert(std::set<Record*>(it->Elements.begin(),
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@ -742,7 +742,7 @@ void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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ie = SingletonRegisterNames.end(); it != ie; ++it)
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if (Record *Rec = getRegisterRecord(Target, *it))
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RegisterSets.insert(std::set<Record*>(&Rec, &Rec + 1));
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// Introduce derived sets where necessary (when a register does not determine
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// a unique register set class), and build the mapping of registers to the set
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// they should classify to.
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@ -752,7 +752,7 @@ void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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CodeGenRegister &CGR = *it;
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// Compute the intersection of all sets containing this register.
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std::set<Record*> ContainingSet;
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for (std::set< std::set<Record*> >::iterator it = RegisterSets.begin(),
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ie = RegisterSets.end(); it != ie; ++it) {
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if (!it->count(CGR.TheDef))
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@ -800,7 +800,7 @@ void AsmMatcherInfo::BuildRegisterClasses(CodeGenTarget &Target,
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ClassInfo *CI = RegisterSetClasses[*it];
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for (std::set< std::set<Record*> >::iterator it2 = RegisterSets.begin(),
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ie2 = RegisterSets.end(); it2 != ie2; ++it2)
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if (*it != *it2 &&
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if (*it != *it2 &&
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std::includes(it2->begin(), it2->end(), it->begin(), it->end()))
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CI->SuperClasses.push_back(RegisterSetClasses[*it2]);
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}
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@ -847,12 +847,12 @@ void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass");
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// Pre-populate AsmOperandClasses map.
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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ie = AsmOperands.end(); it != ie; ++it)
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AsmOperandClasses[*it] = new ClassInfo();
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unsigned Index = 0;
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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for (std::vector<Record*>::iterator it = AsmOperands.begin(),
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ie = AsmOperands.end(); it != ie; ++it, ++Index) {
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ClassInfo *CI = AsmOperandClasses[*it];
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CI->Kind = ClassInfo::UserClass0 + Index;
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@ -880,7 +880,7 @@ void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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if (StringInit *SI = dynamic_cast<StringInit*>(PMName)) {
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CI->PredicateMethod = SI->getValue();
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} else {
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assert(dynamic_cast<UnsetInit*>(PMName) &&
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assert(dynamic_cast<UnsetInit*>(PMName) &&
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"Unexpected PredicateMethod field!");
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CI->PredicateMethod = "is" + CI->ClassName;
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}
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@ -900,7 +900,7 @@ void AsmMatcherInfo::BuildOperandClasses(CodeGenTarget &Target) {
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}
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}
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AsmMatcherInfo::AsmMatcherInfo(Record *_AsmParser)
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AsmMatcherInfo::AsmMatcherInfo(Record *_AsmParser)
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: AsmParser(_AsmParser),
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CommentDelimiter(AsmParser->getValueAsString("CommentDelimiter")),
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RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix"))
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@ -911,10 +911,10 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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// Parse the instructions; we need to do this first so that we can gather the
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// singleton register classes.
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std::set<std::string> SingletonRegisterNames;
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const std::vector<const CodeGenInstruction*> &InstrList =
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Target.getInstructionsByEnumValue();
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for (unsigned i = 0, e = InstrList.size(); i != e; ++i) {
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const CodeGenInstruction &CGI = *InstrList[i];
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@ -922,7 +922,7 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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continue;
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OwningPtr<InstructionInfo> II(new InstructionInfo());
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II->InstrName = CGI.TheDef->getName();
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II->Instr = &CGI;
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II->AsmString = FlattenVariants(CGI.AsmString, 0);
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@ -944,17 +944,17 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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for (unsigned i = 0, e = II->Tokens.size(); i != e; ++i) {
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if (!II->Tokens[i].startswith(RegisterPrefix))
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continue;
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StringRef RegName = II->Tokens[i].substr(RegisterPrefix.size());
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Record *Rec = getRegisterRecord(Target, RegName);
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if (!Rec) {
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// If there is no register prefix (i.e. "%" in "%eax"), then this may
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// be some random non-register token, just ignore it.
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if (RegisterPrefix.empty())
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continue;
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std::string Err = "unable to find register for '" + RegName.str() +
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std::string Err = "unable to find register for '" + RegName.str() +
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"' (which matches register prefix)";
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throw TGError(CGI.TheDef->getLoc(), Err);
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}
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@ -999,14 +999,14 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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for (std::vector<InstructionInfo*>::iterator it = Instructions.begin(),
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ie = Instructions.end(); it != ie; ++it) {
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InstructionInfo *II = *it;
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// The first token of the instruction is the mnemonic, which must be a
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// simple string.
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assert(!II->Tokens.empty() && "Instruction has no tokens?");
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StringRef Mnemonic = II->Tokens[0];
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assert(Mnemonic[0] != '$' &&
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(RegisterPrefix.empty() || !Mnemonic.startswith(RegisterPrefix)));
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// Parse the tokens after the mnemonic.
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for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) {
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StringRef Token = II->Tokens[i];
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@ -1025,7 +1025,7 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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}
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if (!RegisterPrefix.empty()) {
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std::string Err = "unable to find register for '" + RegName.str() +
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std::string Err = "unable to find register for '" + RegName.str() +
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"' (which matches register prefix)";
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throw TGError(II->Instr->TheDef->getLoc(), Err);
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}
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@ -1052,7 +1052,7 @@ void AsmMatcherInfo::BuildInfo(CodeGenTarget &Target) {
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try {
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Idx = II->Instr->getOperandNamed(OperandName);
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} catch(...) {
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throw std::string("error: unable to find operand: '" +
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throw std::string("error: unable to find operand: '" +
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OperandName.str() + "'");
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}
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@ -1122,10 +1122,10 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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OS << "// Unified function for converting operants to MCInst instances.\n\n";
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OS << "enum ConversionKind {\n";
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// TargetOperandClass - This is the target's operand class, like X86Operand.
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std::string TargetOperandClass = Target.getName() + "Operand";
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for (std::vector<InstructionInfo*>::const_iterator it = Infos.begin(),
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ie = Infos.end(); it != ie; ++it) {
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InstructionInfo &II = **it;
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@ -1156,7 +1156,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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unsigned NumMIOperands = 0;
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for (unsigned i = 0, e = II.Instr->OperandList.size(); i != e; ++i) {
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const CodeGenInstruction::OperandInfo &OI = II.Instr->OperandList[i];
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NumMIOperands = std::max(NumMIOperands,
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NumMIOperands = std::max(NumMIOperands,
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OI.MIOperandNo + OI.MINumOperands);
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}
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@ -1167,7 +1167,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second];
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assert(CurIndex <= Op.OperandInfo->MIOperandNo &&
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"Duplicate match for instruction operand!");
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// Skip operands which weren't matched by anything, this occurs when the
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// .td file encodes "implicit" operands as explicit ones.
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//
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@ -1244,12 +1244,12 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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}
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CvtOS << " ((" << TargetOperandClass << "*)Operands["
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<< MIOperandList[i].second
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<< "+1])->" << Op.Class->RenderMethod
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<< MIOperandList[i].second
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<< "+1])->" << Op.Class->RenderMethod
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<< "(Inst, " << Op.OperandInfo->MINumOperands << ");\n";
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CurIndex += Op.OperandInfo->MINumOperands;
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}
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// And add trailing implicit operands.
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for (; CurIndex != NumMIOperands; ++CurIndex) {
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std::pair<unsigned, unsigned> *Tie = GetTiedOperandAtIndex(TiedOperands,
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@ -1279,7 +1279,7 @@ static void EmitConvertToMCInst(CodeGenTarget &Target,
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OS << " NumConversionVariants\n";
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OS << "};\n\n";
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OS << CvtOS.str();
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}
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@ -1293,7 +1293,7 @@ static void EmitMatchClassEnumeration(CodeGenTarget &Target,
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<< "/// instruction matching.\n";
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OS << "enum MatchClassKind {\n";
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OS << " InvalidMatchClass = 0,\n";
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for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
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for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
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ie = Infos.end(); it != ie; ++it) {
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ClassInfo &CI = **it;
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OS << " " << CI.Name << ", // ";
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@ -1332,16 +1332,16 @@ static void EmitClassifyOperand(CodeGenTarget &Target,
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OS << " if (Operand.isReg()) {\n";
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OS << " switch (Operand.getReg()) {\n";
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OS << " default: return InvalidMatchClass;\n";
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for (std::map<Record*, ClassInfo*>::iterator
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for (std::map<Record*, ClassInfo*>::iterator
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it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end();
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it != ie; ++it)
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OS << " case " << Target.getName() << "::"
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OS << " case " << Target.getName() << "::"
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<< it->first->getName() << ": return " << it->second->Name << ";\n";
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OS << " }\n";
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OS << " }\n\n";
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// Classify user defined operands.
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for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
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for (std::vector<ClassInfo*>::iterator it = Info.Classes.begin(),
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ie = Info.Classes.end(); it != ie; ++it) {
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ClassInfo &CI = **it;
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@ -1360,7 +1360,7 @@ static void EmitClassifyOperand(CodeGenTarget &Target,
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OS << "\n";
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OS << " if (Operand." << CI.PredicateMethod << "()) {\n";
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// Validate subclass relationships.
|
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if (!CI.SuperClasses.empty()) {
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for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i)
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@ -1387,13 +1387,13 @@ static void EmitIsSubclass(CodeGenTarget &Target,
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OS << " switch (A) {\n";
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OS << " default:\n";
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OS << " return false;\n";
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for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
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for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
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ie = Infos.end(); it != ie; ++it) {
|
||||
ClassInfo &A = **it;
|
||||
|
||||
if (A.Kind != ClassInfo::Token) {
|
||||
std::vector<StringRef> SuperClasses;
|
||||
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
||||
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
||||
ie = Infos.end(); it != ie; ++it) {
|
||||
ClassInfo &B = **it;
|
||||
|
||||
@ -1431,7 +1431,7 @@ static void EmitMatchTokenString(CodeGenTarget &Target,
|
||||
raw_ostream &OS) {
|
||||
// Construct the match list.
|
||||
std::vector<StringMatcher::StringPair> Matches;
|
||||
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
||||
for (std::vector<ClassInfo*>::iterator it = Infos.begin(),
|
||||
ie = Infos.end(); it != ie; ++it) {
|
||||
ClassInfo &CI = **it;
|
||||
|
||||
@ -1463,11 +1463,11 @@ static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
|
||||
Reg.TheDef->getValueAsString("AsmName"),
|
||||
"return " + utostr(i + 1) + ";"));
|
||||
}
|
||||
|
||||
|
||||
OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
|
||||
|
||||
StringMatcher("Name", Matches, OS).Emit();
|
||||
|
||||
|
||||
OS << " return 0;\n";
|
||||
OS << "}\n\n";
|
||||
}
|
||||
@ -1528,10 +1528,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
// deterministically ordered.
|
||||
std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(),
|
||||
less_ptr<InstructionInfo>());
|
||||
|
||||
|
||||
DEBUG_WITH_TYPE("instruction_info", {
|
||||
for (std::vector<InstructionInfo*>::iterator
|
||||
it = Info.Instructions.begin(), ie = Info.Instructions.end();
|
||||
for (std::vector<InstructionInfo*>::iterator
|
||||
it = Info.Instructions.begin(), ie = Info.Instructions.end();
|
||||
it != ie; ++it)
|
||||
(*it)->dump();
|
||||
});
|
||||
@ -1543,7 +1543,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
for (unsigned j = i + 1; j != e; ++j) {
|
||||
InstructionInfo &A = *Info.Instructions[i];
|
||||
InstructionInfo &B = *Info.Instructions[j];
|
||||
|
||||
|
||||
if (A.CouldMatchAmiguouslyWith(B)) {
|
||||
errs() << "warning: ambiguous instruction match:\n";
|
||||
A.dump();
|
||||
@ -1555,7 +1555,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
}
|
||||
}
|
||||
if (NumAmbiguous)
|
||||
errs() << "warning: " << NumAmbiguous
|
||||
errs() << "warning: " << NumAmbiguous
|
||||
<< " ambiguous instructions!\n";
|
||||
});
|
||||
|
||||
@ -1579,9 +1579,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
<< " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n";
|
||||
OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
OS << "\n#ifdef GET_REGISTER_MATCHER\n";
|
||||
OS << "#undef GET_REGISTER_MATCHER\n\n";
|
||||
|
||||
@ -1592,7 +1592,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
EmitMatchRegisterName(Target, AsmParser, OS);
|
||||
|
||||
OS << "#endif // GET_REGISTER_MATCHER\n\n";
|
||||
|
||||
|
||||
|
||||
OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
|
||||
OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
|
||||
@ -1621,8 +1621,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
Info.Instructions.begin(), ie = Info.Instructions.end();
|
||||
it != ie; ++it)
|
||||
MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size());
|
||||
|
||||
|
||||
|
||||
|
||||
// Emit the static match table; unused classes get initalized to 0 which is
|
||||
// guaranteed to be InvalidMatchClass.
|
||||
//
|
||||
@ -1641,7 +1641,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n";
|
||||
OS << " unsigned RequiredFeatures;\n";
|
||||
OS << " };\n\n";
|
||||
|
||||
|
||||
OS << "// Predicate for searching for an opcode.\n";
|
||||
OS << " struct LessOpcode {\n";
|
||||
OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
|
||||
@ -1654,28 +1654,28 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n";
|
||||
OS << " }\n";
|
||||
OS << " };\n";
|
||||
|
||||
|
||||
OS << "} // end anonymous namespace.\n\n";
|
||||
|
||||
|
||||
OS << "static const MatchEntry MatchTable["
|
||||
<< Info.Instructions.size() << "] = {\n";
|
||||
|
||||
|
||||
for (std::vector<InstructionInfo*>::const_iterator it =
|
||||
Info.Instructions.begin(), ie = Info.Instructions.end();
|
||||
it != ie; ++it) {
|
||||
InstructionInfo &II = **it;
|
||||
|
||||
|
||||
OS << " { " << Target.getName() << "::" << II.InstrName
|
||||
<< ", \"" << II.Tokens[0] << "\""
|
||||
<< ", " << II.ConversionFnKind << ", { ";
|
||||
for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) {
|
||||
InstructionInfo::Operand &Op = II.Operands[i];
|
||||
|
||||
|
||||
if (i) OS << ", ";
|
||||
OS << Op.Class->Name;
|
||||
}
|
||||
OS << " }, ";
|
||||
|
||||
|
||||
// Write the required features mask.
|
||||
if (!II.RequiredFeatures.empty()) {
|
||||
for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) {
|
||||
@ -1684,10 +1684,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
}
|
||||
} else
|
||||
OS << "0";
|
||||
|
||||
|
||||
OS << "},\n";
|
||||
}
|
||||
|
||||
|
||||
OS << "};\n\n";
|
||||
|
||||
// Finally, build the match function.
|
||||
@ -1740,18 +1740,18 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " std::pair<const MatchEntry*, const MatchEntry*> MnemonicRange =\n";
|
||||
OS << " std::equal_range(MatchTable, MatchTable+"
|
||||
<< Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n";
|
||||
|
||||
|
||||
OS << " // Return a more specific error code if no mnemonics match.\n";
|
||||
OS << " if (MnemonicRange.first == MnemonicRange.second)\n";
|
||||
OS << " return Match_MnemonicFail;\n\n";
|
||||
|
||||
|
||||
OS << " for (const MatchEntry *it = MnemonicRange.first, "
|
||||
<< "*ie = MnemonicRange.second;\n";
|
||||
OS << " it != ie; ++it) {\n";
|
||||
|
||||
OS << " // equal_range guarantees that instruction mnemonic matches.\n";
|
||||
OS << " assert(Mnemonic == it->Mnemonic);\n";
|
||||
|
||||
|
||||
// Emit check that the subclasses match.
|
||||
OS << " bool OperandsValid = true;\n";
|
||||
OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n";
|
||||
@ -1767,7 +1767,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " OperandsValid = false;\n";
|
||||
OS << " break;\n";
|
||||
OS << " }\n\n";
|
||||
|
||||
|
||||
OS << " if (!OperandsValid) continue;\n";
|
||||
|
||||
// Emit check that the required features are available.
|
||||
@ -1776,7 +1776,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " HadMatchOtherThanFeatures = true;\n";
|
||||
OS << " continue;\n";
|
||||
OS << " }\n";
|
||||
|
||||
|
||||
OS << "\n";
|
||||
OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
|
||||
|
||||
@ -1793,6 +1793,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
|
||||
OS << " if (HadMatchOtherThanFeatures) return Match_MissingFeature;\n";
|
||||
OS << " return Match_InvalidOperand;\n";
|
||||
OS << "}\n\n";
|
||||
|
||||
|
||||
OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user