diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index bb31fc7f5c8..7b976fce3df 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -80,10 +80,6 @@ namespace { setOperationAction(ISD::MEMSET , MVT::Other, Expand); setOperationAction(ISD::MEMCPY , MVT::Other, Expand); - // We don't support these yet. - setOperationAction(ISD::FNEG , MVT::f64 , Expand); - setOperationAction(ISD::FABS , MVT::f64 , Expand); - computeRegisterProperties(); addLegalFPImmediate(+0.0); @@ -794,7 +790,21 @@ assert(0 && "hmm, ISD::SIGN_EXTEND: shouldn't ever be reached. bad luck!\n"); BuildMI(BB, IA64::FSUB, 2, Result).addReg(Tmp1).addReg(Tmp2); return Result; } - + + case ISD::FABS: { + Tmp1 = SelectExpr(N.getOperand(0)); + assert(DestType == MVT::f64 && "trying to fabs something other than f64?"); + BuildMI(BB, IA64::FABS, 1, Result).addReg(Tmp1); + return Result; + } + + case ISD::FNEG: { + Tmp1 = SelectExpr(N.getOperand(0)); + assert(DestType == MVT::f64 && "trying to fneg something other than f64?"); + BuildMI(BB, IA64::FNEG, 1, Result).addReg(Tmp1); + return Result; + } + case ISD::AND: { switch (N.getValueType()) { default: assert(0 && "Cannot AND this type!"); diff --git a/lib/Target/IA64/IA64InstrInfo.td b/lib/Target/IA64/IA64InstrInfo.td index 6103a375fbd..60166ab9e0f 100644 --- a/lib/Target/IA64/IA64InstrInfo.td +++ b/lib/Target/IA64/IA64InstrInfo.td @@ -227,6 +227,10 @@ def FMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), "fma $dst = $src1, $src2, $src3;;">; def FNMA : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3), "fnma $dst = $src1, $src2, $src3;;">; +def FABS : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), + "fabs $dst = $src;;">; +def FNEG : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src), + "fneg $dst = $src;;">; def CFMAS1 : AForm<0x03, 0x0b, (ops FP:$dst, FP:$src1, FP:$src2, FP:$src3, PR:$qp),