6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-11-02 07:11:49 +00:00
Code Issues Projects Releases Wiki Activity

Add override to overriden virtual methods, remove virtual keywords.

Browse Source 
No functionality change. Changes made by clang-tidy + some manual cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217028 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Benjamin Kramer 2014-09-03 11:41:21 +00:00
parent 8f2394e5af
commit a80ff26688
31 changed files with 73 additions and 101 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/MC/MCObjectStreamer.h
View File

@ -126,7 +126,7 @@ public:
void EmitZeros(uint64_t NumBytes) override;
void FinishImpl() override;
virtual bool mayHaveInstructions() const {
bool mayHaveInstructions() const override {
return getCurrentSectionData()->hasInstructions();
}
};

8
include/llvm/Support/CrashRecoveryContext.h
View File

@ -166,9 +166,7 @@ public:
: CrashRecoveryContextCleanupBase<
CrashRecoveryContextDeleteCleanup<T>, T>(context, resource) {}
virtual void recoverResources() {
delete this->resource;
}
void recoverResources() override { delete this->resource; }
};
template <typename T>
@ -181,9 +179,7 @@ public:
: CrashRecoveryContextCleanupBase<CrashRecoveryContextReleaseRefCleanup<T>,
T>(context, resource) {}
virtual void recoverResources() {
this->resource->Release();
}
void recoverResources() override { this->resource->Release(); }
};
template <typename T, typename Cleanup = CrashRecoveryContextDeleteCleanup<T> >

2
include/llvm/Target/TargetInstrInfo.h
View File

@ -688,7 +688,7 @@ public:
}
/// useMachineCombiner - return true when a target supports MachineCombiner
virtual bool useMachineCombiner(void) const { return false; }
virtual bool useMachineCombiner() const { return false; }
protected:
/// foldMemoryOperandImpl - Target-dependent implementation for

24
lib/Analysis/ScopedNoAliasAA.cpp
View File

@ -80,15 +80,13 @@ public:
initializeScopedNoAliasAAPass(*PassRegistry::getPassRegistry());
}
virtual void initializePass() {
InitializeAliasAnalysis(this);
}
void initializePass() override { InitializeAliasAnalysis(this); }
/// getAdjustedAnalysisPointer - This method is used when a pass implements
/// an analysis interface through multiple inheritance. If needed, it
/// should override this to adjust the this pointer as needed for the
/// specified pass info.
virtual void *getAdjustedAnalysisPointer(const void *PI) {
void *getAdjustedAnalysisPointer(const void *PI) override {
if (PI == &AliasAnalysis::ID)
return (AliasAnalysis*)this;
return this;
@ -100,15 +98,15 @@ protected:
SmallPtrSetImpl<const MDNode *> &Nodes) const;
private:
virtual void getAnalysisUsage(AnalysisUsage &AU) const;
virtual AliasResult alias(const Location &LocA, const Location &LocB);
virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal);
virtual ModRefBehavior getModRefBehavior(ImmutableCallSite CS);
virtual ModRefBehavior getModRefBehavior(const Function *F);
virtual ModRefResult getModRefInfo(ImmutableCallSite CS,
const Location &Loc);
virtual ModRefResult getModRefInfo(ImmutableCallSite CS1,
ImmutableCallSite CS2);
void getAnalysisUsage(AnalysisUsage &AU) const override;
AliasResult alias(const Location &LocA, const Location &LocB) override;
bool pointsToConstantMemory(const Location &Loc, bool OrLocal) override;
ModRefBehavior getModRefBehavior(ImmutableCallSite CS) override;
ModRefBehavior getModRefBehavior(const Function *F) override;
ModRefResult getModRefInfo(ImmutableCallSite CS,
const Location &Loc) override;
ModRefResult getModRefInfo(ImmutableCallSite CS1,
ImmutableCallSite CS2) override;
};
} // End of anonymous namespace

3
lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h
View File

@ -140,7 +140,8 @@ private:
public:
RuntimeDyldMachOCRTPBase(RTDyldMemoryManager *mm) : RuntimeDyldMachO(mm) {}
void finalizeLoad(ObjectImage &ObjImg, ObjSectionToIDMap &SectionMap) {
void finalizeLoad(ObjectImage &ObjImg,
ObjSectionToIDMap &SectionMap) override {
unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID;
unsigned TextSID = RTDYLD_INVALID_SECTION_ID;
unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID;

2
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h
View File

@ -296,7 +296,7 @@ public:
return ++RelI;
}
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
DEBUG(dumpRelocationToResolve(RE, Value));
const SectionEntry &Section = Sections[RE.SectionID];

2
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h
View File

@ -78,7 +78,7 @@ public:
return ++RelI;
}
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
DEBUG(dumpRelocationToResolve(RE, Value));
const SectionEntry &Section = Sections[RE.SectionID];
uint8_t *LocalAddress = Section.Address + RE.Offset;

2
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h
View File

@ -75,7 +75,7 @@ public:
return ++RelI;
}
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
DEBUG(dumpRelocationToResolve(RE, Value));
const SectionEntry &Section = Sections[RE.SectionID];

2
lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h
View File

@ -61,7 +61,7 @@ public:
return ++RelI;
}
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
DEBUG(dumpRelocationToResolve(RE, Value));
const SectionEntry &Section = Sections[RE.SectionID];
uint8_t *LocalAddress = Section.Address + RE.Offset;

4
lib/MC/MCMachOStreamer.cpp
View File

@ -90,8 +90,8 @@ public:
unsigned ByteAlignment) override;
void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = nullptr,
uint64_t Size = 0, unsigned ByteAlignment = 0) override;
virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
uint64_t Size, unsigned ByteAlignment = 0) override;
void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, uint64_t Size,
unsigned ByteAlignment = 0) override;
void EmitFileDirective(StringRef Filename) override {
// FIXME: Just ignore the .file; it isn't important enough to fail the

2
lib/Target/AArch64/AArch64ISelLowering.h
View File

@ -426,7 +426,7 @@ private:
SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
std::vector<SDNode *> *Created) const;
std::vector<SDNode *> *Created) const override;
ConstraintType
getConstraintType(const std::string &Constraint) const override;

2
lib/Target/AArch64/AArch64InstrInfo.cpp
View File

@ -2206,7 +2206,7 @@ void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
NopInst.addOperand(MCOperand::CreateImm(0));
}
/// useMachineCombiner - return true when a target supports MachineCombiner
bool AArch64InstrInfo::useMachineCombiner(void) const {
bool AArch64InstrInfo::useMachineCombiner() const {
// AArch64 supports the combiner
return true;
}

12
lib/Target/AArch64/AArch64InstrInfo.h
View File

@ -161,20 +161,20 @@ public:
/// for an instruction chain ending in <Root>. All potential patterns are
/// listed
/// in the <Pattern> array.
virtual bool hasPattern(
MachineInstr &Root,
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const;
bool hasPattern(MachineInstr &Root,
SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern)
const override;
/// genAlternativeCodeSequence - when hasPattern() finds a pattern
/// this function generates the instructions that could replace the
/// original code sequence
virtual void genAlternativeCodeSequence(
void genAlternativeCodeSequence(
MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
SmallVectorImpl<MachineInstr *> &InsInstrs,
SmallVectorImpl<MachineInstr *> &DelInstrs,
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
/// useMachineCombiner - AArch64 supports MachineCombiner
virtual bool useMachineCombiner(void) const;
bool useMachineCombiner() const override;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
private:

5
lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
View File

@ -127,8 +127,9 @@ public:
void printInstruction(const MCInst *MI, raw_ostream &O) override;
bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx, raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
unsigned PrintMethodIdx,
raw_ostream &O) override;
StringRef getRegName(unsigned RegNo) const override {
return getRegisterName(RegNo);
}

2
lib/Target/ARM/ARMSubtarget.h
View File

@ -437,7 +437,7 @@ public:
/// getInstrItins - Return the instruction itineraries based on subtarget
/// selection.
const InstrItineraryData *getInstrItineraryData() const {
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
}

16
lib/Target/Hexagon/HexagonSubtarget.h
View File

@ -58,19 +58,23 @@ public:
/// getInstrItins - Return the instruction itineraries based on subtarget
/// selection.
const InstrItineraryData *getInstrItineraryData() const {
const InstrItineraryData *getInstrItineraryData() const override {
return &InstrItins;
}
const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const HexagonRegisterInfo *getRegisterInfo() const {
const HexagonRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo();
}
const HexagonTargetLowering *getTargetLowering() const { return &TLInfo; }
const HexagonFrameLowering *getFrameLowering() const {
const HexagonTargetLowering *getTargetLowering() const override {
return &TLInfo;
}
const HexagonFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
const HexagonSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
const DataLayout *getDataLayout() const { return &DL; }
const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
const DataLayout *getDataLayout() const override { return &DL; }
HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
StringRef FS);

4
lib/Target/Mips/MipsTargetStreamer.h
View File

@ -163,7 +163,7 @@ public:
void emitDirectiveSetDsp() override;
// PIC support
virtual void emitDirectiveCpload(unsigned RegNo);
void emitDirectiveCpload(unsigned RegNo) override;
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
const MCSymbol &Sym, bool IsReg) override;
@ -209,7 +209,7 @@ public:
void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
// PIC support
virtual void emitDirectiveCpload(unsigned RegNo);
void emitDirectiveCpload(unsigned RegNo) override;
void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
const MCSymbol &Sym, bool IsReg) override;

4
lib/Target/NVPTX/NVPTXISelLowering.h
View File

@ -505,9 +505,7 @@ public:
bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
return true;
}
bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
private:
const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here

2
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
View File

@ -33,7 +33,7 @@ private:
public:
NVPTXReplaceImageHandles();
bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const override {
return "NVPTX Replace Image Handles";

10
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
View File

@ -29,12 +29,10 @@ public:
virtual ~PPCDisassembler() {}
// Override MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
const MemoryObject &region, uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
};
} // end anonymous namespace

20
lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp
View File

@ -24,11 +24,7 @@ namespace {
public:
PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI);
virtual ~PPCELFObjectWriter();
protected:
virtual unsigned getRelocTypeInner(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const;
unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
bool IsPCRel) const override;
@ -42,9 +38,6 @@ PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
Is64Bit ? ELF::EM_PPC64 : ELF::EM_PPC,
/*HasRelocationAddend*/ true) {}
PPCELFObjectWriter::~PPCELFObjectWriter() {
}
static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
const MCFixup &Fixup) {
const MCExpr *Expr = Fixup.getValue();
@ -73,10 +66,9 @@ static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
llvm_unreachable("unknown PPCMCExpr kind");
}
unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const
{
unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup);
// determine the type of the relocation
@ -400,12 +392,6 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
return Type;
}
unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
const MCFixup &Fixup,
bool IsPCRel) const {
return getRelocTypeInner(Target, Fixup, IsPCRel);
}
bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbolData &SD,
unsigned Type) const {
switch (Type) {

2
lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp
View File

@ -80,7 +80,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
}
/// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
/// Outline based on PPCELFObjectWriter::getRelocTypeInner().
/// Outline based on PPCELFObjectWriter::GetRelocType().
static unsigned getRelocType(const MCValue &Target,
const MCFixupKind FixupKind, // from
// Fixup.getKind()

6
lib/Target/R600/AMDGPUISelLowering.h
View File

@ -153,10 +153,8 @@ public:
const SelectionDAG &DAG,
unsigned Depth = 0) const override;
virtual unsigned ComputeNumSignBitsForTargetNode(
SDValue Op,
const SelectionDAG &DAG,
unsigned Depth = 0) const override;
unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
unsigned Depth = 0) const override;
/// \brief Helper function that adds Reg to the LiveIn list of the DAG's
/// MachineFunction.

5
lib/Target/R600/AMDGPUInstrInfo.h
View File

@ -73,11 +73,6 @@ public:
LiveVariables *LV) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const = 0;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
void storeRegToStackSlot(MachineBasicBlock &MBB,

8
lib/Target/R600/AMDGPUPromoteAlloca.cpp
View File

@ -36,11 +36,9 @@ class AMDGPUPromoteAlloca : public FunctionPass,
public:
AMDGPUPromoteAlloca(const AMDGPUSubtarget &st) : FunctionPass(ID), ST(st),
LocalMemAvailable(0) { }
virtual bool doInitialization(Module &M);
virtual bool runOnFunction(Function &F);
virtual const char *getPassName() const {
return "AMDGPU Promote Alloca";
}
bool doInitialization(Module &M) override;
bool runOnFunction(Function &F) override;
const char *getPassName() const override { return "AMDGPU Promote Alloca"; }
void visitAlloca(AllocaInst &I);
};

2
lib/Target/R600/AMDGPURegisterInfo.h
View File

@ -51,7 +51,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
unsigned getSubRegFromChannel(unsigned Channel) const;
const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS) const override;
unsigned getFrameRegister(const MachineFunction &MF) const override;

2
lib/Target/R600/AMDGPUTargetMachine.cpp
View File

@ -80,7 +80,7 @@ public:
return nullptr;
}
virtual void addCodeGenPrepare();
void addCodeGenPrepare() override;
bool addPreISel() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;

4
lib/Target/R600/AMDGPUTargetMachine.h
View File

@ -36,7 +36,9 @@ public:
const AMDGPUSubtarget *getSubtargetImpl() const override {
return &Subtarget;
}
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { return &IntrinsicInfo; }
const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
return &IntrinsicInfo;
}
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
/// \brief Register R600 analysis passes with a pass manager.

2
lib/Target/R600/R600InstrInfo.h
View File

@ -206,7 +206,7 @@ namespace llvm {
int getInstrLatency(const InstrItineraryData *ItinData,
SDNode *Node) const override { return 1;}
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
/// \brief Reserve the registers that may be accesed using indirect addressing.
void reserveIndirectRegisters(BitVector &Reserved,

2
lib/Target/R600/SIInstrInfo.h
View File

@ -87,7 +87,7 @@ public:
const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const override;
virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
unsigned commuteOpcode(unsigned Opcode) const;

11
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
View File

@ -37,13 +37,10 @@ public:
MCDisassembler(STI, Ctx) {}
/// \brief See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
const MemoryObject &region, uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const override;
};
}