Add override to overriden virtual methods, remove virtual keywords.

No functionality change. Changes made by clang-tidy + some manual cleanup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217028 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/MC/MCObjectStreamer.h

@@ -126,7 +126,7 @@ public:
   void EmitZeros(uint64_t NumBytes) override;
   void FinishImpl() override;
 
-  virtual bool mayHaveInstructions() const {
+  bool mayHaveInstructions() const override {
     return getCurrentSectionData()->hasInstructions();
   }
 };

include/llvm/Support/CrashRecoveryContext.h

@@ -166,9 +166,7 @@ public:
     : CrashRecoveryContextCleanupBase<
         CrashRecoveryContextDeleteCleanup<T>, T>(context, resource) {}
 
-  virtual void recoverResources() {
+  void recoverResources() override { delete this->resource; }
-    delete this->resource;
-  }  
 };
 
 template <typename T>
@@ -181,9 +179,7 @@ public:
     : CrashRecoveryContextCleanupBase<CrashRecoveryContextReleaseRefCleanup<T>,
           T>(context, resource) {}
 
-  virtual void recoverResources() {
+  void recoverResources() override { this->resource->Release(); }
-    this->resource->Release();
-  }
 };
 
 template <typename T, typename Cleanup = CrashRecoveryContextDeleteCleanup<T> >

include/llvm/Target/TargetInstrInfo.h

@@ -688,7 +688,7 @@ public:
   }
 
   /// useMachineCombiner - return true when a target supports MachineCombiner
-  virtual bool useMachineCombiner(void) const { return false; }
+  virtual bool useMachineCombiner() const { return false; }
 
 protected:
   /// foldMemoryOperandImpl - Target-dependent implementation for

lib/Analysis/ScopedNoAliasAA.cpp

@@ -80,15 +80,13 @@ public:
     initializeScopedNoAliasAAPass(*PassRegistry::getPassRegistry());
   }
 
-  virtual void initializePass() {
+  void initializePass() override { InitializeAliasAnalysis(this); }
-    InitializeAliasAnalysis(this);
-  }
 
   /// getAdjustedAnalysisPointer - This method is used when a pass implements
   /// an analysis interface through multiple inheritance.  If needed, it
   /// should override this to adjust the this pointer as needed for the
   /// specified pass info.
-  virtual void *getAdjustedAnalysisPointer(const void *PI) {
+  void *getAdjustedAnalysisPointer(const void *PI) override {
     if (PI == &AliasAnalysis::ID)
       return (AliasAnalysis*)this;
     return this;
@@ -100,15 +98,15 @@ protected:
                          SmallPtrSetImpl<const MDNode *> &Nodes) const;
 
 private:
-  virtual void getAnalysisUsage(AnalysisUsage &AU) const;
+  void getAnalysisUsage(AnalysisUsage &AU) const override;
-  virtual AliasResult alias(const Location &LocA, const Location &LocB);
+  AliasResult alias(const Location &LocA, const Location &LocB) override;
-  virtual bool pointsToConstantMemory(const Location &Loc, bool OrLocal);
+  bool pointsToConstantMemory(const Location &Loc, bool OrLocal) override;
-  virtual ModRefBehavior getModRefBehavior(ImmutableCallSite CS);
+  ModRefBehavior getModRefBehavior(ImmutableCallSite CS) override;
-  virtual ModRefBehavior getModRefBehavior(const Function *F);
+  ModRefBehavior getModRefBehavior(const Function *F) override;
-  virtual ModRefResult getModRefInfo(ImmutableCallSite CS,
+  ModRefResult getModRefInfo(ImmutableCallSite CS,
-                                     const Location &Loc);
+                             const Location &Loc) override;
-  virtual ModRefResult getModRefInfo(ImmutableCallSite CS1,
+  ModRefResult getModRefInfo(ImmutableCallSite CS1,
-                                     ImmutableCallSite CS2);
+                             ImmutableCallSite CS2) override;
 };
 }  // End of anonymous namespace
 

lib/ExecutionEngine/RuntimeDyld/RuntimeDyldMachO.h

@@ -140,7 +140,8 @@ private:
 public:
   RuntimeDyldMachOCRTPBase(RTDyldMemoryManager *mm) : RuntimeDyldMachO(mm) {}
 
-  void finalizeLoad(ObjectImage &ObjImg, ObjSectionToIDMap &SectionMap) {
+  void finalizeLoad(ObjectImage &ObjImg,
+                    ObjSectionToIDMap &SectionMap) override {
     unsigned EHFrameSID = RTDYLD_INVALID_SECTION_ID;
     unsigned TextSID = RTDYLD_INVALID_SECTION_ID;
     unsigned ExceptTabSID = RTDYLD_INVALID_SECTION_ID;

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOAArch64.h

@@ -296,7 +296,7 @@ public:
     return ++RelI;
   }
 
-  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
+  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
     DEBUG(dumpRelocationToResolve(RE, Value));
 
     const SectionEntry &Section = Sections[RE.SectionID];

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOARM.h

@@ -78,7 +78,7 @@ public:
     return ++RelI;
   }
 
-  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
+  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
     DEBUG(dumpRelocationToResolve(RE, Value));
     const SectionEntry &Section = Sections[RE.SectionID];
     uint8_t *LocalAddress = Section.Address + RE.Offset;

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOI386.h

@@ -75,7 +75,7 @@ public:
     return ++RelI;
   }
 
-  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
+  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
     DEBUG(dumpRelocationToResolve(RE, Value));
 
     const SectionEntry &Section = Sections[RE.SectionID];

lib/ExecutionEngine/RuntimeDyld/Targets/RuntimeDyldMachOX86_64.h

@@ -61,7 +61,7 @@ public:
     return ++RelI;
   }
 
-  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) {
+  void resolveRelocation(const RelocationEntry &RE, uint64_t Value) override {
     DEBUG(dumpRelocationToResolve(RE, Value));
     const SectionEntry &Section = Sections[RE.SectionID];
     uint8_t *LocalAddress = Section.Address + RE.Offset;

lib/MC/MCMachOStreamer.cpp

@@ -90,8 +90,8 @@ public:
                              unsigned ByteAlignment) override;
   void EmitZerofill(const MCSection *Section, MCSymbol *Symbol = nullptr,
                     uint64_t Size = 0, unsigned ByteAlignment = 0) override;
-  virtual void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol,
+  void EmitTBSSSymbol(const MCSection *Section, MCSymbol *Symbol, uint64_t Size,
-                      uint64_t Size, unsigned ByteAlignment = 0) override;
+                      unsigned ByteAlignment = 0) override;
 
   void EmitFileDirective(StringRef Filename) override {
     // FIXME: Just ignore the .file; it isn't important enough to fail the

lib/Target/AArch64/AArch64ISelLowering.h

@@ -426,7 +426,7 @@ private:
   SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
 
   SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
-                        std::vector<SDNode *> *Created) const;
+                        std::vector<SDNode *> *Created) const override;
 
   ConstraintType
   getConstraintType(const std::string &Constraint) const override;

lib/Target/AArch64/AArch64InstrInfo.cpp

@@ -2206,7 +2206,7 @@ void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
   NopInst.addOperand(MCOperand::CreateImm(0));
 }
 /// useMachineCombiner - return true when a target supports MachineCombiner
-bool AArch64InstrInfo::useMachineCombiner(void) const {
+bool AArch64InstrInfo::useMachineCombiner() const {
   // AArch64 supports the combiner
   return true;
 }

lib/Target/AArch64/AArch64InstrInfo.h

@@ -161,20 +161,20 @@ public:
   /// for an instruction chain ending in <Root>. All potential patterns are
   /// listed
   /// in the <Pattern> array.
-  virtual bool hasPattern(
+  bool hasPattern(MachineInstr &Root,
-      MachineInstr &Root,
+                  SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern)
-      SmallVectorImpl<MachineCombinerPattern::MC_PATTERN> &Pattern) const;
+      const override;
 
   /// genAlternativeCodeSequence - when hasPattern() finds a pattern
   /// this function generates the instructions that could replace the
   /// original code sequence
-  virtual void genAlternativeCodeSequence(
+  void genAlternativeCodeSequence(
       MachineInstr &Root, MachineCombinerPattern::MC_PATTERN P,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
       SmallVectorImpl<MachineInstr *> &DelInstrs,
-      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
+      DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
   /// useMachineCombiner - AArch64 supports MachineCombiner
-  virtual bool useMachineCombiner(void) const;
+  bool useMachineCombiner() const override;
 
   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 private:

lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h

@@ -127,8 +127,9 @@ public:
 
   void printInstruction(const MCInst *MI, raw_ostream &O) override;
   bool printAliasInstr(const MCInst *MI, raw_ostream &O) override;
-  virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
+  void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
-                                       unsigned PrintMethodIdx, raw_ostream &O);
+                               unsigned PrintMethodIdx,
+                               raw_ostream &O) override;
   StringRef getRegName(unsigned RegNo) const override {
     return getRegisterName(RegNo);
   }

lib/Target/ARM/ARMSubtarget.h

@@ -437,7 +437,7 @@ public:
 
   /// getInstrItins - Return the instruction itineraries based on subtarget
   /// selection.
-  const InstrItineraryData *getInstrItineraryData() const {
+  const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
 

lib/Target/Hexagon/HexagonSubtarget.h

@@ -58,19 +58,23 @@ public:
 
   /// getInstrItins - Return the instruction itineraries based on subtarget
   /// selection.
-  const InstrItineraryData *getInstrItineraryData() const {
+  const InstrItineraryData *getInstrItineraryData() const override {
     return &InstrItins;
   }
   const HexagonInstrInfo *getInstrInfo() const override { return &InstrInfo; }
-  const HexagonRegisterInfo *getRegisterInfo() const {
+  const HexagonRegisterInfo *getRegisterInfo() const override {
     return &InstrInfo.getRegisterInfo();
   }
-  const HexagonTargetLowering *getTargetLowering() const { return &TLInfo; }
+  const HexagonTargetLowering *getTargetLowering() const override {
-  const HexagonFrameLowering *getFrameLowering() const {
+    return &TLInfo;
+  }
+  const HexagonFrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
-  const HexagonSelectionDAGInfo *getSelectionDAGInfo() const { return &TSInfo; }
+  const HexagonSelectionDAGInfo *getSelectionDAGInfo() const override {
-  const DataLayout *getDataLayout() const { return &DL; }
+    return &TSInfo;
+  }
+  const DataLayout *getDataLayout() const override { return &DL; }
 
   HexagonSubtarget &initializeSubtargetDependencies(StringRef CPU,
                                                     StringRef FS);

lib/Target/Mips/MipsTargetStreamer.h

@@ -163,7 +163,7 @@ public:
   void emitDirectiveSetDsp() override;
 
   // PIC support
-  virtual void emitDirectiveCpload(unsigned RegNo);
+  void emitDirectiveCpload(unsigned RegNo) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 
@@ -209,7 +209,7 @@ public:
   void emitFMask(unsigned FPUBitmask, int FPUTopSavedRegOff) override;
 
   // PIC support
-  virtual void emitDirectiveCpload(unsigned RegNo);
+  void emitDirectiveCpload(unsigned RegNo) override;
   void emitDirectiveCpsetup(unsigned RegNo, int RegOrOffset,
                             const MCSymbol &Sym, bool IsReg) override;
 

lib/Target/NVPTX/NVPTXISelLowering.h

@@ -505,9 +505,7 @@ public:
 
   bool allowFMA(MachineFunction &MF, CodeGenOpt::Level OptLevel) const;
 
-  virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
+  bool isFMAFasterThanFMulAndFAdd(EVT) const override { return true; }
-    return true;
-  }
 
 private:
   const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here

lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp

@@ -33,7 +33,7 @@ private:
 public:
   NVPTXReplaceImageHandles();
 
-  bool runOnMachineFunction(MachineFunction &MF);
+  bool runOnMachineFunction(MachineFunction &MF) override;
 
   const char *getPassName() const override {
     return "NVPTX Replace Image Handles";

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

@@ -29,12 +29,10 @@ public:
   virtual ~PPCDisassembler() {}
 
   // Override MCDisassembler.
-  virtual DecodeStatus getInstruction(MCInst &instr,
+  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
-                                      uint64_t &size,
+                              const MemoryObject &region, uint64_t address,
-                                      const MemoryObject &region,
+                              raw_ostream &vStream,
-                                      uint64_t address,
+                              raw_ostream &cStream) const override;
-                                      raw_ostream &vStream,
-                                      raw_ostream &cStream) const override;
 };
 } // end anonymous namespace
 

lib/Target/PowerPC/MCTargetDesc/PPCELFObjectWriter.cpp

@@ -24,11 +24,7 @@ namespace {
   public:
     PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI);
 
-    virtual ~PPCELFObjectWriter();
   protected:
-    virtual unsigned getRelocTypeInner(const MCValue &Target,
-                                       const MCFixup &Fixup,
-                                       bool IsPCRel) const;
     unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup,
                           bool IsPCRel) const override;
 
@@ -42,9 +38,6 @@ PPCELFObjectWriter::PPCELFObjectWriter(bool Is64Bit, uint8_t OSABI)
                             Is64Bit ?  ELF::EM_PPC64 : ELF::EM_PPC,
                             /*HasRelocationAddend*/ true) {}
 
-PPCELFObjectWriter::~PPCELFObjectWriter() {
-}
-
 static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
                                                      const MCFixup &Fixup) {
   const MCExpr *Expr = Fixup.getValue();
@@ -73,10 +66,9 @@ static MCSymbolRefExpr::VariantKind getAccessVariant(const MCValue &Target,
   llvm_unreachable("unknown PPCMCExpr kind");
 }
 
-unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
+unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
-                                               const MCFixup &Fixup,
+                                          const MCFixup &Fixup,
-                                               bool IsPCRel) const
+                                          bool IsPCRel) const {
-{
   MCSymbolRefExpr::VariantKind Modifier = getAccessVariant(Target, Fixup);
 
   // determine the type of the relocation
@@ -400,12 +392,6 @@ unsigned PPCELFObjectWriter::getRelocTypeInner(const MCValue &Target,
   return Type;
 }
 
-unsigned PPCELFObjectWriter::GetRelocType(const MCValue &Target,
-                                          const MCFixup &Fixup,
-                                          bool IsPCRel) const {
-  return getRelocTypeInner(Target, Fixup, IsPCRel);
-}
-
 bool PPCELFObjectWriter::needsRelocateWithSymbol(const MCSymbolData &SD,
                                                  unsigned Type) const {
   switch (Type) {

lib/Target/PowerPC/MCTargetDesc/PPCMachObjectWriter.cpp

@@ -80,7 +80,7 @@ static unsigned getFixupKindLog2Size(unsigned Kind) {
 }
 
 /// Translates generic PPC fixup kind to Mach-O/PPC relocation type enum.
-/// Outline based on PPCELFObjectWriter::getRelocTypeInner().
+/// Outline based on PPCELFObjectWriter::GetRelocType().
 static unsigned getRelocType(const MCValue &Target,
                              const MCFixupKind FixupKind, // from
                                                           // Fixup.getKind()

lib/Target/R600/AMDGPUISelLowering.h

@@ -153,10 +153,8 @@ public:
                                      const SelectionDAG &DAG,
                                      unsigned Depth = 0) const override;
 
-  virtual unsigned ComputeNumSignBitsForTargetNode(
+  unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const SelectionDAG &DAG,
-    SDValue Op,
+                                           unsigned Depth = 0) const override;
-    const SelectionDAG &DAG,
-    unsigned Depth = 0) const override;
 
   /// \brief Helper function that adds Reg to the LiveIn list of the DAG's
   /// MachineFunction.

lib/Target/R600/AMDGPUInstrInfo.h

@@ -73,11 +73,6 @@ public:
                         LiveVariables *LV) const override;
 
 
-  virtual void copyPhysReg(MachineBasicBlock &MBB,
-                           MachineBasicBlock::iterator MI, DebugLoc DL,
-                           unsigned DestReg, unsigned SrcReg,
-                           bool KillSrc) const = 0;
-
   bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
   void storeRegToStackSlot(MachineBasicBlock &MBB,

lib/Target/R600/AMDGPUPromoteAlloca.cpp

@@ -36,11 +36,9 @@ class AMDGPUPromoteAlloca : public FunctionPass,
 public:
   AMDGPUPromoteAlloca(const AMDGPUSubtarget &st) : FunctionPass(ID), ST(st),
                                                    LocalMemAvailable(0) { }
-  virtual bool doInitialization(Module &M);
+  bool doInitialization(Module &M) override;
-  virtual bool runOnFunction(Function &F);
+  bool runOnFunction(Function &F) override;
-  virtual const char *getPassName() const {
+  const char *getPassName() const override { return "AMDGPU Promote Alloca"; }
-    return "AMDGPU Promote Alloca";
-  }
   void visitAlloca(AllocaInst &I);
 };
 

lib/Target/R600/AMDGPURegisterInfo.h

@@ -51,7 +51,7 @@ struct AMDGPURegisterInfo : public AMDGPUGenRegisterInfo {
   unsigned getSubRegFromChannel(unsigned Channel) const;
 
   const MCPhysReg* getCalleeSavedRegs(const MachineFunction *MF) const override;
-  virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
+  void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS) const override;
   unsigned getFrameRegister(const MachineFunction &MF) const override;

lib/Target/R600/AMDGPUTargetMachine.cpp

@@ -80,7 +80,7 @@ public:
     return nullptr;
   }
 
-  virtual void addCodeGenPrepare();
+  void addCodeGenPrepare() override;
   bool addPreISel() override;
   bool addInstSelector() override;
   bool addPreRegAlloc() override;

lib/Target/R600/AMDGPUTargetMachine.h

@@ -36,7 +36,9 @@ public:
   const AMDGPUSubtarget *getSubtargetImpl() const override {
     return &Subtarget;
   }
-  const AMDGPUIntrinsicInfo *getIntrinsicInfo() const { return &IntrinsicInfo; }
+  const AMDGPUIntrinsicInfo *getIntrinsicInfo() const override {
+    return &IntrinsicInfo;
+  }
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
 
   /// \brief Register R600 analysis passes with a pass manager.

lib/Target/R600/R600InstrInfo.h

@@ -206,7 +206,7 @@ namespace llvm {
   int getInstrLatency(const InstrItineraryData *ItinData,
                       SDNode *Node) const override { return 1;}
 
-  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
   /// \brief Reserve the registers that may be accesed using indirect addressing.
   void reserveIndirectRegisters(BitVector &Reserved,

lib/Target/R600/SIInstrInfo.h

@@ -87,7 +87,7 @@ public:
                             const TargetRegisterClass *RC,
                             const TargetRegisterInfo *TRI) const override;
 
-  virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
+  bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
 
   unsigned commuteOpcode(unsigned Opcode) const;
 

lib/Target/XCore/Disassembler/XCoreDisassembler.cpp

@@ -37,13 +37,10 @@ public:
     MCDisassembler(STI, Ctx) {}
 
   /// \brief See MCDisassembler.
-  virtual DecodeStatus getInstruction(MCInst &instr,
+  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
-                                      uint64_t &size,
+                              const MemoryObject &region, uint64_t address,
-                                      const MemoryObject &region,
+                              raw_ostream &vStream,
-                                      uint64_t address,
+                              raw_ostream &cStream) const override;
-                                      raw_ostream &vStream,
-                                      raw_ostream &cStream) const override;
-
 };
 }