diff --git a/lib/Target/Sparc/SparcISelLowering.cpp b/lib/Target/Sparc/SparcISelLowering.cpp
index 32e02698f3f..22662c097b8 100644
--- a/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/lib/Target/Sparc/SparcISelLowering.cpp
@@ -2298,12 +2298,16 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
   assert(LdNode && LdNode->getOffset().getOpcode() == ISD::UNDEF
          && "Unexpected node type");
 
+  unsigned alignment = LdNode->getAlignment();
+  if (alignment > 8)
+    alignment = 8;
+
   SDValue Hi64 = DAG.getLoad(MVT::f64,
                              dl,
                              LdNode->getChain(),
                              LdNode->getBasePtr(),
                              LdNode->getPointerInfo(),
-                             false, false, false, 8);
+                             false, false, false, alignment);
   EVT addrVT = LdNode->getBasePtr().getValueType();
   SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
                               LdNode->getBasePtr(),
@@ -2313,7 +2317,7 @@ static SDValue LowerF128Load(SDValue Op, SelectionDAG &DAG)
                              LdNode->getChain(),
                              LoPtr,
                              LdNode->getPointerInfo(),
-                             false, false, false, 8);
+                             false, false, false, alignment);
 
   SDValue SubRegEven = DAG.getTargetConstant(SP::sub_even64, MVT::i32);
   SDValue SubRegOdd  = DAG.getTargetConstant(SP::sub_odd64, MVT::i32);
@@ -2357,13 +2361,18 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
                                     MVT::f64,
                                     StNode->getValue(),
                                     SubRegOdd);
+
+  unsigned alignment = StNode->getAlignment();
+  if (alignment > 8)
+    alignment = 8;
+
   SDValue OutChains[2];
   OutChains[0] = DAG.getStore(StNode->getChain(),
                               dl,
                               SDValue(Hi64, 0),
                               StNode->getBasePtr(),
                               MachinePointerInfo(),
-                              false, false, 8);
+                              false, false, alignment);
   EVT addrVT = StNode->getBasePtr().getValueType();
   SDValue LoPtr = DAG.getNode(ISD::ADD, dl, addrVT,
                               StNode->getBasePtr(),
@@ -2373,7 +2382,7 @@ static SDValue LowerF128Store(SDValue Op, SelectionDAG &DAG) {
                              SDValue(Lo64, 0),
                              LoPtr,
                              MachinePointerInfo(),
-                             false, false, 8);
+                             false, false, alignment);
   return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
                      &OutChains[0], 2);
 }
diff --git a/test/CodeGen/SPARC/fp128.ll b/test/CodeGen/SPARC/fp128.ll
index 2406af753fa..789e074d917 100644
--- a/test/CodeGen/SPARC/fp128.ll
+++ b/test/CodeGen/SPARC/fp128.ll
@@ -126,3 +126,24 @@ entry:
   store fp128 %0, fp128* %scalar.result, align 8
   ret void
 }
+
+; HARD-LABEL: fp128_unaligned
+; HARD:       ldub
+; HARD:       faddq
+; HARD:       stb
+; HARD:       jmp
+
+; SOFT-LABEL: fp128_unaligned
+; SOFT:       ldub
+; SOFT:       call _Q_add
+; SOFT:       stb
+; SOFT:       jmp
+
+define void @fp128_unaligned(fp128* %a, fp128* %b, fp128* %c) {
+entry:
+  %0 = load fp128* %a, align 1
+  %1 = load fp128* %b, align 1
+  %2 = fadd fp128 %0, %1
+  store fp128 %2, fp128* %c, align 1
+  ret void
+}