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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-08-09 11:25:55 +00:00
Support fp64 immediate zero, this fixes only part of PR5445
because the testcase is triggering one more bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88674 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -314,6 +314,16 @@ SDNode* MipsDAGToDAGISel::Select(SDValue N) {
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case ISD::GLOBAL_OFFSET_TABLE:
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case ISD::GLOBAL_OFFSET_TABLE:
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return getGlobalBaseReg();
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return getGlobalBaseReg();
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
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if (N.getValueType() == MVT::f64 && CN->isExactlyValue(+0.0)) {
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SDValue Zero = CurDAG->getRegister(Mips::ZERO, MVT::i32);
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ReplaceUses(N, Zero);
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return Zero.getNode();
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}
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break;
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}
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/// Handle direct and indirect calls when using PIC. On PIC, when
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/// Handle direct and indirect calls when using PIC. On PIC, when
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/// GOT is smaller than about 64k (small code) the GA target is
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/// GOT is smaller than about 64k (small code) the GA target is
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/// loaded with only one instruction. Otherwise GA's target must
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/// loaded with only one instruction. Otherwise GA's target must
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@@ -134,6 +134,9 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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DebugLoc DL = DebugLoc::getUnknownLoc();
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const MachineFunction *MF = MBB.getParent();
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const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC != SrcRC) {
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if (DestRC != SrcRC) {
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@@ -153,6 +156,13 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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else if ((DestRC == Mips::FGR32RegisterClass) &&
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else if ((DestRC == Mips::FGR32RegisterClass) &&
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(SrcRC == Mips::CPURegsRegisterClass))
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(SrcRC == Mips::CPURegsRegisterClass))
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BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
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else if ((DestRC == Mips::AFGR64RegisterClass) &&
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(SrcRC == Mips::CPURegsRegisterClass) &&
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(SrcReg == Mips::ZERO)) {
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const unsigned *AliasSet = TRI->getAliasSet(DestReg);
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BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[0]).addReg(SrcReg);
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BuildMI(MBB, I, DL, get(Mips::MTC1), AliasSet[1]).addReg(SrcReg);
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}
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// Move from/to Hi/Lo registers
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// Move from/to Hi/Lo registers
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else if ((DestRC == Mips::HILORegisterClass) &&
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else if ((DestRC == Mips::HILORegisterClass) &&
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@@ -163,9 +173,8 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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(DestRC == Mips::CPURegsRegisterClass)) {
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(DestRC == Mips::CPURegsRegisterClass)) {
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unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
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unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
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BuildMI(MBB, I, DL, get(Opc), DestReg);
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BuildMI(MBB, I, DL, get(Opc), DestReg);
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} else
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// Can't copy this register
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// Can't copy this register
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} else
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return false;
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return false;
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return true;
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return true;
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