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recognize ppc's blr instruction as predicated

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31480 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-11-06 21:44:54 +00:00
parent 1b1b737d7d
commit a818e92f8b
3 changed files with 4 additions and 0 deletions
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1
utils/TableGen/CodeGenInstruction.h
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@ -87,6 +87,7 @@ namespace llvm {
bool isLoad;
bool isStore;
bool isTwoAddress;
bool isPredicated;
bool isConvertibleToThreeAddress;
bool isCommutable;
bool isTerminator;

2
utils/TableGen/CodeGenTarget.cpp
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@ -335,6 +335,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
isLoad = R->getValueAsBit("isLoad");
isStore = R->getValueAsBit("isStore");
isTwoAddress = R->getValueAsBit("isTwoAddress");
isPredicated = false; // set below.
isConvertibleToThreeAddress = R->getValueAsBit("isConvertibleToThreeAddress");
isCommutable = R->getValueAsBit("isCommutable");
isTerminator = R->getValueAsBit("isTerminator");
@ -381,6 +382,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
if (unsigned NumArgs = MIOpInfo->getNumArgs())
NumOps = NumArgs;
isPredicated |= Rec->isSubClassOf("PredicateOperand");
} else if (Rec->getName() == "variable_ops") {
hasVariableNumberOfOperands = true;
continue;

1
utils/TableGen/InstrInfoEmitter.cpp
View File

@ -225,6 +225,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
if (Inst.isLoad) OS << "|M_LOAD_FLAG";
if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
if (Inst.isPredicated) OS << "|M_PREDICATED";
if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
if (Inst.isCommutable) OS << "|M_COMMUTABLE";
if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";